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Thread: Teensy 4.1 LCD output

  1. #1
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    Teensy 4.1 LCD output

    Hi everyone,

    I was looking at the rt1060 datasheet and there is an LCD controller. Sadly, the parallel lcd data bus run through the GPIO B0_xx and B1_xx (for wider buses).
    So my question is if it possible to directly diver fast big (>10") screens with 800x600 resolutions with the Teensy? I have only found smaller (both in size and res) displays with serial connection and onboard memory.
    Sorry if this has been answered before, I searched on the forums with negative results.

    Thank you for your help!

  2. #2
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    Ok, after further investigation, it seems that a possible solution would be to use to use the Ra8876 lcd driver. Does anyone knows how fast the lcd can be drive? is there a fps limitation? does the RA8876 access a framebuffer through DMA?

  3. #3
    Senior Member+ KurtE's Avatar
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    I just started to play with the 7" variation of a display with RA8876. More information on a few different threads, including: https://forum.pjrc.com/threads/58565...sy-T36-and-T40

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    Thanks KurtE, I will order the 7" display and start tinkering around. Hopefully I will be able to join the thread before you guys have figured everything out

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    Hi. Quick question:
    When you say: Sadly, the parallel lcd data bus run through the GPIO B0_xx and B1_xx (for wider buses) > do you mean that there is no way to use the built in lcd contrôler due to pins not routed ?

  6. #6
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    That was my impression. Take this with a pinch of salt as I am just a software guy new to Teensy. But looking at the schematics (https://www.pjrc.com/teensy/schematic.html) and the rt1062 datasheet, we need the whole B0 and part of B1 ports for the embedded parallel LCD controller. Even if we just use it as an 8bit parallel RGB interface we still miss B0_04 to B0_11 (page 1842 from https://www.pjrc.com/teensy/IMXRT1060RM_rev2.pdf)

  7. #7
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    As mentioned not all of the IO pins associated with that interface is not exposed by the T4 or T4.1... SO yes you probably can not use that interface... (Note I am a software guy as well)

    But that does not necessarily imply you can not use a display that uses parallel interface. I have not done it, as I mostly play with SPI...

    I have no idea of what display you are/were thinking of trying, so not sure how easy it would be to do... I believe some others have done such.

    There are a few different approaches to outputting the parallel data.

    a) try to find one CPU GPIO register that has all of the pins needed hopefully consecutively, where you can simply output them directly. With all of the caveats of maybe have to split it up or do some fancy bit rearranging...

    b) maybe can do one bit at a time, for the registers.... Easiest to attempt but probably not very fast.

    c) Look at FlexIO. There is a whole section in the PDF file on this. The new T4.1 has more of these pins brought out, and there are a few different threads talking about this.
    I have a github project where I have tried out bits and pieces, like classes that can create some Serial Ports, and some SPI stuff... And one that did do some parallel stuff if I remember correctly.
    Some of the details of what I have experimented with are up on my github project: https://github.com/KurtE/FlexIO_t4

    Excerpt from Readme about 4.1
    Code:
    The Teensy 4.1 Will have additional IO pins.
    
    Warning The below now matches the first update to github CORE project for T4.1 by Paul, so the final pin numbers are probably reasonably close, but probably not written in stone until the boards actually start shipping. So maybe take it with grain of salt.
    
    FlexIO 1 - The three rows are: Teensy pin, Flex IO pin, and MUX setting for that pin:
    
        2,       3,    4,    5,  33,    49,   50,   52,   54
        4,       5,    6,    8,  7,     13,   14,   12,   15
        0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14
    
    Ranges: 4-8,12-15
    
    FlexIO 2
    
        6,       7,    8,    9,  10,    11,   12,   13,   32,   34,   35,   36,   37
        10,     17,   16,   11,  0,      2,    1,    3,   12,   29,   28,   18,   19
        0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14
    
    So have bit ranges 0-3, 10-12, 16-19, 28029
    
    FlexIO 3 - Note Flex IO 3 does not have DMA support
    
        7,       8,   14,   15,   16,   17,   18,   19,   20,  21,    22,   23,   26,   27,   34,   35,   36,   37,   38,   39,   40,   41
        17,     16,    2,    3,    7,    6,    1,    0,   10,   11,    8,    9,   14,   15,   29,   28,   18,   19,   12,   13,    4,    5 
        0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19 
    
    Have ranges: 0-19, 28-29

  8. #8
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    Hi there. The whole purpose of the tft interface is to be able to cope with slightly larger tft than 320x480. Sizes like that or smaller have built in frame buffer and the writing speed through even a small interface like spi will have no effect on the actual frame rate. With larger screens, like a sunreadable 480x480 has typically no built in frame buffer and then pclk needs to be regular and synced to h and v sync...
    maybe teensy 4.2 will have proper tft pins exposed + some more psram sockets :-)

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    Thank KurtE for pointing me to the FlexIO feature, you gave me something to learn about, the example for a 68K or 8080 16 bit interface seems promising, although a bit cryptic.
    My requirements for an LCD are 800x600x16bit at 30Hz. Also, for simplicity, I would like to double buffer which translates to a memory requirement of almost 2MB (I guess need to order some of those PSRAM)
    Having to transmit 800x600x2B on a 16bit bus at 30Hz seems I would need to drive the bus at least at 15MHz which I guess is doable (not a clue from an electronic perspective if at this speed I need to terminate the bus in any special way to keep the signal integrity)
    Hobi: memory wise seem a single 8MB would be enough (bring back memories from my earlier PCs . Worst case scenario, using external memory + RA8876 I think it could work, given the RA8876 can DMA from serial memory.

  10. #10
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    Hmmm really interesting. Let’s see what we can get out of flexio...

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  12. #12
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    Thanks Hobi for the app note . I am ordering some displays today, the 7" with the RA8876 and a 800x600 with just a parallel rgb interface, both from buydisplay. Hopefully I can test some things before those arrives.

  13. #13
    I have used the FlexIO with 16bit parallel interface, based on the mculcd demo from the NXP SDK.

    It works well, although I did have to tweak it a bit.

  14. #14
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    Quote Originally Posted by JKIM View Post
    I have used the FlexIO with 16bit parallel interface, based on the mculcd demo from the NXP SDK.
    Hi JKIM, did you used it with the Teensy? what type of display where you driving?

  15. #15
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    Quote Originally Posted by JKIM View Post
    I have used the FlexIO with 16bit parallel interface, based on the mculcd demo from the NXP SDK.

    It works well, although I did have to tweak it a bit.
    Wish to share... Might be fun to add an example to my FlexIO library of the like.

  16. #16
    I am using a custom board (with FlexIO2), but it looks like the standard T4.1 should have enough exposed consecutive pins on FlexIO3 starting with AD_B1_00 for the 16bit bus, plus 4 pins for D/C, WR, and CS.

    The example I started with is here: https://community.nxp.com/thread/501529

    But using the NXP SDK drivers is a bit of a rabbit hole to use with T4, you have to fix a bunch of defines, etc.

  17. #17
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    @Glaskows, this is what you look for I think, but in 16 bits :
    https://www.nxp.com/docs/en/application-note/AN5313.pdf

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    Has anyone else tried the 16bit parallel interface with the T4.1?
    It would be interesting to see how it performs against the SPI-DMA libraries by Kurt.

  19. #19
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    Sounds like fun. But a couple of things to watch out for. AFAIK there is no direct way to do DMA with FLEXIO3, there are 2 each for FLEXIO1 and FLEXIO2:
    Code:
    #define DMAMUX_SOURCE_FLEXIO1_REQUEST0		0
    #define DMAMUX_SOURCE_FLEXIO1_REQUEST1		0
    #define DMAMUX_SOURCE_FLEXIO2_REQUEST0		1
    #define DMAMUX_SOURCE_FLEXIO2_REQUEST1		1
    ...
    #define DMAMUX_SOURCE_FLEXIO1_REQUEST2		64
    #define DMAMUX_SOURCE_FLEXIO1_REQUEST3		64
    #define DMAMUX_SOURCE_FLEXIO2_REQUEST2		65
    #define DMAMUX_SOURCE_FLEXIO2_REQUEST3		65
    Note in the above list you have one DMAMUX_SOURCE for two FLEXIO shifter (or was it timer)... So you need to sometimes pick carefully which flex IO piece you wish to use...

  20. #20
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    Kurt I was under the impression that only FLEXIO3 could be used as all it's GPIO's on the same port register.
    But, if we can combine FLEXIO1 & FLEXIO2 with DMA that could be ideal, no?

    I saw this video of a T3.6 driving a 800x480 display over 16 bit parallel interface and it looks darn quick. I know the T4/4.1 uses a different chipset than the 3.6 but still found it interesting


    Please do educate me on this

  21. #21
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    Good luck...

    The available on T4 and 4.1 are shown up on my github project: https://github.com/KurtE/FlexIO_t4

    And it looks like some others have had some success...

    Personally there are many other distractions on my list that grab my interest, so it could be a long while before I get tempted to jump into this one

  22. #22
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    Quote Originally Posted by Rezo View Post
    Kurt I was under the impression that only FLEXIO3 could be used as all it's GPIO's on the same port register.
    But, if we can combine FLEXIO1 & FLEXIO2 with DMA that could be ideal, no?

    I saw this video of a T3.6 driving a 800x480 display over 16 bit parallel interface and it looks darn quick. I know the T4/4.1 uses a different chipset than the 3.6 but still found it interesting


    Please do educate me on this

    Hi.

    I intend to drive a 16 bit LCD 480x480 with an Hsync/Vsync/pixel clock interface, RGB 565, using Flexio 3 on T4.1. Reason why I plan on using Flexio3 rather than the 1 and 2 flexios is I need to transcode RGB 8 bit to 16 bit on the fly, while reading from frame buffer , and write to LCD interface. The CPU will have to do that. it means that the Interrupt task will contain the transoding code, and fill up Flexio3 pipeline as needed.

    I will give it a try.

  23. #23
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    Quote Originally Posted by hobi View Post
    Hi.

    I intend to drive a 16 bit LCD 480x480 with an Hsync/Vsync/pixel clock interface, RGB 565, using Flexio 3 on T4.1. Reason why I plan on using Flexio3 rather than the 1 and 2 flexios is I need to transcode RGB 8 bit to 16 bit on the fly, while reading from frame buffer , and write to LCD interface. The CPU will have to do that. it means that the Interrupt task will contain the transoding code, and fill up Flexio3 pipeline as needed.

    I will give it a try.
    Sounds interesting!
    I have some bare ILI9488 displays that can be driven either SPI, DBI or RGB(as you plan to) that I can also test on. Happy to try it out once you have something built up

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