LaurentNorbert
Member
Hello,
I am using the digital audio output (toslink) of a TV and I want the sound to be played on one of my Teensy 3.6 DACs. The stereo will come later.
I got the code from @gfvalvo,(https://forum.pjrc.com/threads/45394-SPDIF-Input-and-Output?highlight=s/pdif) and I use the same device as him (WM8804 S/PDIF and IIS/I2S Audio Signal Transceiver).
The device is in master mode and the Teensy is in slave mode for the I2S connection.
Question: on the WM8804, there are the connections
LRCLK <-> pin 23
BCLK <-> pin 9
DOUT <-> pin 13
GND <-> GND (!)
* 5V_IN not connected, the WM8804 already being powered
* MCLK not connected (because Teensy in slave mode)
Is that correct?
Seemingly, the LRCLK signal is re-used as a clock for the DAC.
In gfvalvo's code, is the LRCLK signal reused on pin 29 of the Teensy?
I have a doubt because of the method:
void AudioOutputAnalogSyncLRCLK::enableDmaRequest() {
// Enable PIN29 to trigger DMA
// Call this during setup() after we're sure AudioInputWM8804Slave constructor has run
CORE_PIN23_CONFIG |= PORT_PCR_IRQC(2); // pin 29, PTC10, I2S0_RX_FS
}
PIN23 or PIN29?
I admit that I don't master the concepts of DMA and I don't know the Teensy port registers (I come from the Arduino's world).
Another difficulty will certainly come from the fact that the TV signal is sampled at 48 kHz from what I understand.
However, my main concern is that no signal comes out of the DAC at the moment.
Any help is welcome!
I am using the digital audio output (toslink) of a TV and I want the sound to be played on one of my Teensy 3.6 DACs. The stereo will come later.
I got the code from @gfvalvo,(https://forum.pjrc.com/threads/45394-SPDIF-Input-and-Output?highlight=s/pdif) and I use the same device as him (WM8804 S/PDIF and IIS/I2S Audio Signal Transceiver).
The device is in master mode and the Teensy is in slave mode for the I2S connection.
Question: on the WM8804, there are the connections
LRCLK <-> pin 23
BCLK <-> pin 9
DOUT <-> pin 13
GND <-> GND (!)
* 5V_IN not connected, the WM8804 already being powered
* MCLK not connected (because Teensy in slave mode)
Is that correct?
Seemingly, the LRCLK signal is re-used as a clock for the DAC.
In gfvalvo's code, is the LRCLK signal reused on pin 29 of the Teensy?
I have a doubt because of the method:
void AudioOutputAnalogSyncLRCLK::enableDmaRequest() {
// Enable PIN29 to trigger DMA
// Call this during setup() after we're sure AudioInputWM8804Slave constructor has run
CORE_PIN23_CONFIG |= PORT_PCR_IRQC(2); // pin 29, PTC10, I2S0_RX_FS
}
PIN23 or PIN29?
I admit that I don't master the concepts of DMA and I don't know the Teensy port registers (I come from the Arduino's world).
Another difficulty will certainly come from the fact that the TV signal is sampled at 48 kHz from what I understand.
However, my main concern is that no signal comes out of the DAC at the moment.
Any help is welcome!