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Thread: Teensy 4.1 flash/psram usage

  1. #1
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    Teensy 4.1 flash/psram usage

    Is there support and/or examples of using the backside flash/psram memory on the Teensy 4.1? Or a list of what the Auduino pin number are for the memories. I'm new to this and not sure how to map the pins on the schematic to the Arduino "pin" numbers. I need to add a chunk of flash to the 4.1 for some permanent storage and I didn't want to mess around with SD cards.

    Thanks!

  2. #2
    Senior Member+ defragster's Avatar
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    There are posts - probably T_4.1 beta thread - that show what pin numbers are associated with the QSPI pad groups on the T_4.1.

    But unless using for direct I/O - the MCU knows what to do with those pins running example code below like SPIFFS.

    If using the linked and listed PSRAM chip ( only one 8 MB chip seen/tested as also sold by PJRC ) - when mounted on the smaller spaced pads it will be active and ready for direct memory addressing on entering setup(). Those addresses are in samples - Paul posted a RAM test - that may be on a 1.52 Beta thread.

    Did a QSPI search and this post appeared - didn't open :: Question-about-Teensy-4-1-memory-pads

    There are posts - it seems a thread - about locating sources for the PSRAM chip

    The larger spaced pads can hold another PSRAM or Winbond 16 MB Flash as tested. If a 2nd PSRAM it linearly extends that QSPI memory of the first.

    If FLASH :: it requires init code and is direct access readable - but writes must use necessary 'helper code' to assure it is formatted and then written. There are code examples for both in the SPIFFS related library noted in the forum and hosted here : github.com/PaulStoffregen/teensy41_extram

  3. #3
    Senior Member+ KurtE's Avatar
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    I have posted information about the back pins on a few different threads, including links to my excel document and PDFs I created from it...

    Here is an image showing the information about all of the pins. I posted this recently, although this one was updated after that point, to change the PWM columns, to instead of just showing a "P" or PWM for a pin being PWM, it now shows the actual Timer Port, PIN, SUBPORT information, as I often need more information than just a pin is PWM...

    Click image for larger version. 

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    Probably should add a bunch of information like this to unofficial WIKI.

  4. #4
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    How do you setup the SPI2 to use the pins associated with the backside pads on the T4.1? I'd like to put an FRAM chip on the pads intended for the flash memory chip. The pin assignments are identical, but I don't know how to assign SPI2 function to those pins (shown in red type on your image).

    Thanks in advance for your help.

  5. #5
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    Just FYI
    Here is what I found for the (wider) flash memory pin pads:
    function = digital pin, chip pin
    /CS = 51 , 1
    SO (MISO) = 49 , 2
    /WP = 50 , 3
    Vss = GND , 4
    SI (MOSI) = 52 , 5
    SCK = 53 , 6
    /HOLD or RESET = 54 , 7
    Vdd = 3.3 VDC , 8

    and the PSRAM pin pads:
    /CS = 48 , 1
    SO (MISO) = 49 , 2
    /WP = 50 , 3
    Vss = GND, 4
    SI (MOSI) = 52 , 5
    SCK = 53 , 6
    /HOLD or RESET = 54 , 7
    Vdd = 3.3 VDC , 8

    I just used the "blink" program with the digital values above and a multimeter to figure it out. After that I was able use an FRAM chip on the flash pads and just bit banged the SPI. This doesn't seem to match what is on KurtE's (please check me I good at being wrong) map, but it worked for me. Hopefully it is helpful.
    Last edited by SR61; 06-19-2020 at 11:40 PM.

  6. #6
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by SR61 View Post
    How do you setup the SPI2 to use the pins associated with the backside pads on the T4.1? I'd like to put an FRAM chip on the pads intended for the flash memory chip. The pin assignments are identical, but I don't know how to assign SPI2 function to those pins (shown in red type on your image).

    Thanks in advance for your help.
    In startup.c PJRC pings the QSPI pins for a known PSRAM device - so looking in there with show that - when found it sets the external_psram_size in configure_external_ram()
    > is the FRAM a QSPI capable device?
    If so that will help it speedwise - when the right setup is done properly for that device if supported. For the PSRAM it ends up mapping 100% into memory space for read/write once that config is done.

  7. #7
    Senior Member+ KurtE's Avatar
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    @SR61, glad you got it working for you...

    With the card I posted it is always fun to figure out what subset of the information to post. Example this is from another tab in the same excel document, for thos pins:
    Code:
    SD Pins - Cable connector(T4 34-39)												
    42	SD_B0_03	2.15	Serial5(8) RTS		SPI2(1) MISO	PWM1_B1			IO-07			DATA1
    43	SD_B0_02	3.14	Serial5(8) CTS		SPI2(1) MOSI	PWM1_A1			IO-06			DATA0
    44	SD_B0_01	3.13		Wire1(3) SDA	SPI2(1) CS0	PWM1_B0			IO-05			CLK
    45	SD_B0_00	3.12		Wire1(3) SCL	SPI2(1) SCK	PWM1_A0			IO-04			CMD
    46	SD_B0_05	3.17	Serial5(8) RX		FLEXSPI B_DQS	PWM1_B2			IO-09			DATA3
    47	SD_B0_04	3.16	Serial5(8) TX		FLEXSPI B_SSO_B	PWM1_A2			IO-08			DATA2
    Bottom Memory Connectors												
    48	EMC_24	4:24	Serial8(5) RX 		FLEXSPI2_A_SS0_B	PWM1_B0						
    49	EMC_27	4:27	Serial8(5) RTS		FLEXSPI2_A_DATA01, SPI2(1) SCK  	PWM1_A2				1:13		
    50	EMC_28	4:28	Serial8(5) CTS		FLEXSPI2_A_DATA02, SPI2(1) MOSI	PWM1_B2				1:14		
    51	EMC_22	4:22		Wire1(3) SCL	FLEXSPI2_A_SS1_B	PWM3_B3, QT2_3						
    52	EMC_26	4:26	Serial1(6) RX 		FLEXSPI2_A_DATA00	PWM1_B1				1:12		
    53	EMC_25	4:25	Serial1(6) TX 		FLEXSPI2_A_SCLK	PWM1_A1						
    54	EMC_29	4:29	Serial1(6) RTS		FLEXSPI2_A_DATA03, SPI2(1) MISO	PWM3_A0				1:15
    The fun thing here is there are two completely different SPI systems involved on these pins.

    That is These pins are setup to use FLexSPI subsystem: Chapter 26 of the IMXRT1060RM.pdf file. Which after reading it a few times, I think I need to read it several more times before it makes total sense. So in the above these pins are setup to use FlexSPI2 object and you see all of these pins have roles in the FlexSPI2. As you mentioned pin 51 can be configured for FLEXSPI2_A_SS1_B which is a form of chip select...

    Note @Paul added code into the core files (startup.c) which automatically tries to configure these pins into SPI2 and detect if there is a PSRAM installed and is then part of the addressable memory space.


    But in addition, if you are not using it to have a PSRAM or Flash each of these pins can be configured for other things including what most of us think of as SPI which is the LPSPI subsystem, which is what I am showing in the Card view.. That is it is using the underlying object LPSPI1 which in the SPI library is the SPI2 object. In the above table you will also see that the pins in the SDCard can also be configured as SPI2 pins....

    If you want even more of the gory details, you can look at the first couple of pins mentioned:
    like Pin 51 is internally EMC_22, if you look for EMC_22 in the IOMUXC_ chapter (10), you will find at about page 448, the register:
    IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
    Code:
    MUX Mode Select Field.
    Select one of iomux modes to be used for pad: GPIO_EMC_22.
    000 ALT0 — Select mux mode: ALT0 mux port: SEMC_BA1 of instance: semc
    001 ALT1 — Select mux mode: ALT1 mux port: FLEXPWM3_PWMB03 of instance: flexpwm3
    010 ALT2 — Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: lpi2c3
    011 ALT3 — Select mux mode: ALT3 mux port: ENET_TDATA00 of instance: enet
    100 ALT4 — Select mux mode: ALT4 mux port: QTIMER2_TIMER3 of instance: qtimer2
    101 ALT5 — Select mux mode: ALT5 mux port: GPIO4_IO22 of instance: gpio4
    1000 ALT8 — Select mux mode: ALT8 mux port: FLEXSPI2_A_SS1_B of instance: flexspi2
    So for FlexSPI2 you configure the pin into ALT8... And there are not LPSPI functions on this pin.

    But if you look at pins 49 which is EMC_27 - IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 (P453)
    Code:
    000 ALT0 — Select mux mode: ALT0 mux port: SEMC_CKE of instance: semc
    001 ALT1 — Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1
    010 ALT2 — Select mux mode: ALT2 mux port: LPUART5_RTS_B of instance: lpuart5
    011 ALT3 — Select mux mode: ALT3 mux port: LPSPI1_SCK of instance: lpspi1
    100 ALT4 — Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO13 of instance: flexio1
    101 ALT5 — Select mux mode: ALT5 mux port: GPIO4_IO27 of instance: gpio4
    1000 ALT8 — Select mux mode: ALT8 mux port: FLEXSPI2_A_DATA01 of instance: flexspi2
    Again you will see ALT8 sets up for FlexSPI2, and in this case ALT3 sets it up as SCK for LPSPI1...

    Again sorry if this is too much information, but thought it be helpful to some to see where this data comes from.

    Also let me know if you do find errors in my tables and the like as I have found a few just a few days ago with the PWM markings.

  8. #8
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    @KurtE and Defragster

    Thanks for the very quick and thorough replies. The FRAM is only an SPI not QSPI device ( Cypress CY15B108QN 8 Mbit ). The pinout matches the WS25Q128. Because I couldn't figure out how to write to the WS25Q128 I tried the FRAM which I had used in other projects.
    I failed to recognized the distinction pointed out by KurtE, that the SPI2 and QSPI functions were not mapped the same. So I completely misinterpreted the information.
    I have been enthusiastic about the Teensy 4.1 because it has so much memory, and I was really happy to see the flash memory pads, but I can't seem to figure out writing to flash yet so I settled for what I knew (FRAM).

    Thanks again to both of you for helping me out! I really appreciate it.

  9. #9
    Senior Member PaulStoffregen's Avatar
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    The main problem with using CY15B108QN on the FlexSPI2 port is the clock speed. We currently configure FlexSPI2 for 88 MHz clock. Future versions might increase the clock to 132 MHz.

    But CY15B108QN supports only up to 40 MHz.

    Click image for larger version. 

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    I'm not sure how to get around this problem. The slowest we've ever used is 49.5 MHz. I do not know how to configure it to run slower. Maybe there's some way if one of the PLL PFDs is reprogrammed for a slower base clock?

    If the clock speed problem could be solved, then the "only" issue is reprogramming the FlexSPI LUTs to perform single data pin access rather than 4 pins.

  10. #10
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    What are the implications of the 88 MHz clock? I'm assuming this means that messages sent to or read from PSRAM at 88 MHz? How does this interact with the base 600 MHz clock speed of the IMXRT1062?

    I ran the PSRAM test and everything worked out. (I have two PSRAM IC's soldered onto the 4.1).

    Is there a convenient way to test how much PSRAM is being used by a program/process in real-time? I'm curious about this since intend to run tensor flow lite on the 4.1. I read some critiques on the 4.0 with regard to machine learning applications, primarily due to the lack of ram on that board (https://www.stupid-projects.com/tens...on-teensy-4-0/). I wonder what correlations can be drawn for ram usage versus processing performance. It would be an interesting benchmark to contrast teensy 4.0 with teensy 4.1 (I also have teensy 4.0, so I could certainly test it

    Any info will be appreciated. I'm rather new at this.

  11. #11
    Senior Member+ defragster's Avatar
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    The PSRAM with QSPI interface has direct processor support for reading and writing into the memory space. It has a check for existence in startup.c - when found it is currently configured to work at 88 MHz. The processor handles I/O requests to the address space assigned to the chip(s) as needed - including carrying data in the cache as it chooses for faster access when the cache contains or can hold data.

    The I/O operations will cause processor waits as needed. The SPIFFS/extRam thread and library has code that sets the QSPI access to 132 MHz where it has been well tested - but set to 88 MHz to assure users didn't get issues with alternate chips.

    As noted the PSRAM maps directly to the Teensy ARM address space - but currently there is no native use of that area. It is up to the user to access that space and do the needed tracking of used or unused space. Some version of a malloc() or other dynamic allocation will likely be done in future. There is a thread where KurtE did a quick generic mock up allocate only version ( no delete or garbage collection ) IIRC.

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