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Thread: NAND flash support in 1.54

  1. #151
    Senior Member+ mjs513's Avatar
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    Quote Originally Posted by ecurtz View Post
    This is how I understand it. Any of this could be wrong.

    On the 1062 side
    CAS is where the 1062 divides a 32 bit address into the column and the page.
    The value in the LUT defines how many bits are actually sent, so if it's larger than CAS for a CADDR_SDR command (or larger than 32 - CAS for a ADDR_SDR) it will be 0 padded.

    On the NAND side
    Each page contains 2048 bytes of data plus 64 bytes of ECC data.
    Any column address with bit 11 set isn't addressing data, it's addressing the ECC block after the data, so e.g.
    address 2050 (0b1000 0000 0000 0010) isn't byte 2 in page 1, it's part of the page 0 ECC

    If this is correct then any scheme that tries to use continuous addresses without some kind of accommodation for the ECC regions is going to break. By setting CAS to 11 I believe we can work around that, with the potential downside that we can't directly access the ECC data areas, but that shouldn't be necessary if the onboard ECC is enabled for the chip.
    Ok you convinced me its back to 11

  2. #152
    Senior Member+ mjs513's Avatar
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    Alcon
    Was rummaging around and looking for Filesystems for NAND and came across this: https://github.com/ARMmbed/littlefs/issues/361 on using littleFS. Just a interesting post.

  3. #153
    Senior Member+ defragster's Avatar
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    Lots of chatter there ending in RTOS - that could just be an implementation detail.

    just got adaF NRF's that have 2 MB QSPI NOR Flash - they seem to refer to littleFS usage - though no examples for Arduino yet detected on QSPI. Not sure if it is active in the adaPython? The sample I did find seems to use a 28KB area on the main flash? Of course their NRF Arduino code includes some part of RTOS - in order to use the MCU for radio tasks.

  4. #154
    Senior Member+ mjs513's Avatar
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    Been doing some more reading (always a mistake for me) on NAND filesystems. Thought i would share here.
    1. Interesting presentation on whats on there by Toshiba: https://elinux.org/images/9/9a/CELFJ...FS-Toshiba.pdf
    2. This one was a similar question on StackExchange: https://electronics.stackexchange.co...icrocontroller

    There are also pros and cons of using SPIFFS and FatFs it seems.

  5. #155
    After my patented "see what's on GitHub" search process I also thought dhara looked interesting, but whatever Paul is planning in terms of the new file abstraction might make a big difference in the best way to approach a higher level NAND API.

  6. #156
    Senior Member+ KurtE's Avatar
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    I have also sort have been holding off on this, as again not sure where many of these things are going.

    Hopefully we can come up with some maybe scalable ways of using more of these storage areas. Where hopefully some of them are KISS, but maybe allows the sketch an easy api to store and retrieve data, and maybe simple way to likewise save and retrieve the data over USB (in same sketch)... Also hopefully that some of this will be consistent for a few different memory options, like: in this case NAND and NOR (maybe SD?), also maybe for those of us who for example sketches may not exceed 4MB (probably less than 2), maybe a way to reserve a portion of the ROM (like we do for EEPROM) for extended storage...

  7. #157
    Senior Member+ mjs513's Avatar
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    Dhara is actually one of links in the second reference as well. I agree it does look interesting. But, as you said, think we have to wait until Paul decides on the abstraction layer he wants to use. In other reading saw that SPIFFs are probably not best suited for NAND's for a couple of reasons.

  8. #158
    Senior Member+ mjs513's Avatar
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    @KurtE
    Agreed. So now time me to ramble.

    Right now we showed accessing a NAND (1Gb) is possible and you can read and write to it. But with out a FS, in my opinion, its really not all that useable. NAND is going to be a challenge. For instance I tried writing to the same page 10 times using 20byte blocks of data but it will not work. If i write chunks of 512kb of data 4 times (4 subpages) to a single page it works. Writing larger data buffers across pages, works from what I can see. Then with NAND you have to worry about wear leveling and ECC handling. So for NAND not sure how simple we are going to be able to keep it without a FS. Guess it depends on you application. NOR is probably better for some cases.

  9. #159
    I am trying to use this chip also but with standard SPI so I made a new thread.
    Any experts please have a look,
    https://forum.pjrc.com/threads/62226...178#post248178

    Thanks

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