teensy 3.2 scl speed

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Fox95

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i am using a logic analyze to measure speed of the i2c bus, but need some help. its supposed be operating at 400khz


this is in the code:
Wire.begin(I2C_MASTER, 0x00, I2C_PINS_18_19, I2C_PULLUP_EXT, 400000); // Wire bus, SCL pin 19, SDA pin 18, ext pullup, 400kHz


can someone look at these logic analyzer screen shots and tell me is its working at the correct speed?
thanks

scl speed.jpg


sdaspeed.jpg
 
here's the logic analyzer capture file if that helps.

thanks
 

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  • SCLSDASPEED_24 MHz, 24 M Samples [4].zip
    1.1 MB · Views: 43
Just reading the displayed first image on SCL clock line - looks like it suggests f=375KHz, so freq is toward but not beyond 400KHz
 
Yes. I saw that. Any ideas as to why its slower than the 400 requested?

Digital divider math for setting the clock given the available base clock freq. A given clock and freq feed that hardware. It gets divided down to the 'suggested' with the best binary bits available without going over.
 
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