description of pins wrong?

[madGambol]

Hi,
In reading the Teensy docs (https://www.pjrc.com/teensy/pins.html), I found this statement: 'You can also implement an "open collector" output by loading a zero into the PORTx register and then using the DDRx register to output low or allow the pin to "float".'

That language is confusing to me. Is there an open collector mode the GPIO pins support? Does outputting "low or allow the pin to float" mean outputting "low allows the pin to float"? or that you can output low (to sink current as an open collector would do) OR output a high to allow the pin to float.

If outputting a low causes the pin to float (it can go high through a pull up resistor), then that's an inversion of the bit. That mode of operation isn't covered by selecting the pin to be input or output.

I haven't looked at the part spec to see if there's an actual open collector mode.

Just wondering.

madGambol

 

[MarkT]

Hi,
In reading the Teensy docs (https://www.pjrc.com/teensy/pins.html), I found this statement: 'You can also implement an "open collector" output by loading a zero into the PORTx register and then using the DDRx register to output low or allow the pin to "float".'

That language is confusing to me. Is there an open collector mode the GPIO pins support? Does outputting "low or allow the pin to float" mean outputting "low allows the pin to float"? or that you can output low (to sink current as an open collector would do) OR output a high to allow the pin to float.

Those comments are only relevant to Atmel Teensy's (2.x and before I think).

In the Atmel you can toggle the DDR (data direction register) bits to switch between floating and driving (ie INPUT and OUTPUT). If the
relevant PORT bit is low, then the DDR bit will toggle the pin between floating and driving low, which is like open-collector.

Its not open-collector though, as the output voltage cannot rise above the supply due to the protection diodes on the pin. And
its open-drain really as there's no BJT involved (!).

Other processor architectures have different low level register schemes for pin control, most will allow this pseudo-open-collector
behaviour because its useful for bussed signals like I2C.