Greetings,
This is my first post about the excellent Teensy devices. I', not sure if I should put it here or in "Suggestions".
I am editing the HardwareSerial class to expose the TX and RX ringbuffers (rx_buffer1 and rx_buffer1 etc.) that implement the serial FIFO buffers to my code. This is for Teensy 4.x devices. Why?
Before I do this, I thought I'd canvas any opinions out there...
Best wishes to all
Chris
This is my first post about the excellent Teensy devices. I', not sure if I should put it here or in "Suggestions".
I am editing the HardwareSerial class to expose the TX and RX ringbuffers (rx_buffer1 and rx_buffer1 etc.) that implement the serial FIFO buffers to my code. This is for Teensy 4.x devices. Why?
- I use my own ringbuffers in my code to interface the multiple HardwareSerial ports to a software router fabric also connected to other interfaces
- The HardwareSerial ports are running at many megabaud
- Shunting data between the HardwareSerial ringbuffers and mine with HardwareSerial::Read and ::Write is wasting a lot of much needed CPU cycles that is hammering performance, I can only partially fix this with fine-tuned threading. Having two sets of buffers also wastes a lot of memory...
Before I do this, I thought I'd canvas any opinions out there...
- Are there any gotchas to this?
- If I did a tidy job of it, would there be interest in having a patch pushed in to the source tree, or should I just keep my ugly hacks to myself?
Best wishes to all
Chris