[posted] VGA out for Teensy 4.0/4.1

DE could be done from the interrupts but pixelcloxk is more tricky with my limited knowledge of the shift registers hw
 
Jean-Marc said:
DE could be done from the interrupts but pixelcloxk is more tricky with my limited knowledge of the shift registers hw
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I'd be happy to have your "limited knowledge" any day! I love your work.

Anyway, building on what Frank says in his comments, might there just be a way to route your video pll5 clock (at 25.175 MHz) to SAI2 or SAI3 and out to a pin via i2s's mclk? As you've stated in other posts, the pll audio and video are similar.

Jon
 
Jean-Marc said:
The vga driver has a 320x240 framebuffer. You can always scale up your 120x160 to this resolution.
JM
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Hi Jean-Marc,
ok for buffer I understand that I can reduce resolution range.


But whats about PAL signal generation output?

thank's for your reply.

regards
Laurent.
 
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