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Thread: Teensy 4.x max DMA throughput

  1. #1
    Join Date
    Nov 2015

    Teensy 4.x max DMA throughput

    I realize that the IMXRT1062 reference manual probably has this info buried in it, but I'm hoping that someone has already worked out what I'd like to know or can point me to where I should start reading.

    I am interested in interfacing 2 high speed parallel bus (mapped to consecutive GPIO pins) external A/D's to the Teensy 4.1 and would like to know what the maximum theoretical throughput would be for one channel and for two simultaneous channels. I could clock one channel on the rising and the other on the falling edge of a shared clock if that would help. I would also think that using the internal DMA FIFO byte/word packing should help throughput. In addition, I wonder if the 1062 could support simultaneous peripheral DMA to different internal memory areas, and if that might minimize RAM contention and improve two channel bandwidth.

    My ideal would be to support two channels at 50 MHz each for a combined peripheral to memory throughput of 100 MHz.

    I would appreciate any pertinent thoughts or suggestions as to sources of info.

  2. #2
    Senior Member
    Join Date
    May 2015
    A good question - 50 Mhz ADC on a teensy seems feasible and interesting. I/O ports are slow (don't use figures from memory->memory DMA), so maybe not 100 Mhz?

    Maybe better to trigger the DMA from "conversion complete" on the ADC. And transfer the data from both converters in a single operation.

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