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Thread: Maximum bit limit on Teensy 4.1 for Audio purpose

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  1. #1

    Maximum bit limit on Teensy 4.1 for Audio purpose

    Hey all.

    I am working on a hobby project at home and i was curious about what the maximum bit limit is for Teensy 4.1?
    In the datasheet for Teensy 4.1, it is interpreted that it can run 32 bits for 32 channels, but it does not say exactly if it can or not, so i am little bit confused.

    Thanks for the help.

  2. #2
    Senior Member PaulStoffregen's Avatar
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    NXP's documentation is indeed confusing. I don't even really know the answer to this question. Maybe Frank will chime in, but I would be a bit surprised if he answered with 100% certainty. The reality is (as far as I know) nobody has really tested this yet.

    So far the most we do with the audio library is TDM using a 256 bit frame (16 channels, 16 bits each). That is the most I can say with 100% confidence does indeed work. Both ports support that format and can definitely be used in parallel, for a total of 32 channels, 16 bits each, both input and output.

    Stepping this up to a 512 bit frame seems like it should be possible. We're currently setting I2S_TCR4_FRSZ and I2S_RCR4_FRSZ to 7 (meaning 8 words of 32 bits), and it can theoretically go up to 31 (for 32 of those words). But a larger frame at the same sample rate would require a faster BCLK. Currently we're setting I2S_TCR2_DIV & I2S_RCR2_DIV to zero (fastest possible), so you'd need to edit the PLL clock divider to get a higher base clock. However, the datasheet says 25 MHz is the maximum for BCLK, so I don't see how you could use more than 512 bits per frame at 44.1 or 48 kHz sample rate. Theoretically a 1024 bit frame should be possible, but the BCLK hardware speed limit means you could only do with at 24 kHz sample rate (if such a large frame really works at all).

    But it might be possible to use 2 parallel TDM frames of 512 bits (on the first port only - SAI2 only supports 1 transmit and 1 receive data pin), if more of the bits in I2S2_TCR3 and I2S2_RCR3 are set. Again, that's guesswork. It definitely does work with I2S protocol, so odds are good that would give 2 TDM streams like we get with quad (2 strereo) I2S. Together with a 512 bit frame size, you could potentially get 3 transmit pins and 3 receive pins with that 512 bit frame by using both SAI1 (2 data pins) & SAI2 (1 data pin).

    What hardware you would connect is a mystery to me. All the TDM chips I've see expect at most a 256 bit frame. That's the reason we support a fixed 256 bit frame with the TDM code in the audio library (and on Teensy 3.x the BCLK spec is 12.5 MHz max). But maybe chips supporting larger frames exist? Or maybe you're planning to roll your own with a FPGA?

  3. #3
    Quote Originally Posted by PaulStoffregen View Post
    NXP's documentation is indeed confusing. I don't even really know the answer to this question. Maybe Frank will chime in, but I would be a bit surprised if he answered with 100% certainty. The reality is (as far as I know) nobody has really tested this yet.

    So far the most we do with the audio library is TDM using a 256 bit frame (16 channels, 16 bits each). That is the most I can say with 100% confidence does indeed work. Both ports support that format and can definitely be used in parallel, for a total of 32 channels, 16 bits each, both input and output.

    Stepping this up to a 512 bit frame seems like it should be possible. We're currently setting I2S_TCR4_FRSZ and I2S_RCR4_FRSZ to 7 (meaning 8 words of 32 bits), and it can theoretically go up to 31 (for 32 of those words). But a larger frame at the same sample rate would require a faster BCLK. Currently we're setting I2S_TCR2_DIV & I2S_RCR2_DIV to zero (fastest possible), so you'd need to edit the PLL clock divider to get a higher base clock. However, the datasheet says 25 MHz is the maximum for BCLK, so I don't see how you could use more than 512 bits per frame at 44.1 or 48 kHz sample rate. Theoretically a 1024 bit frame should be possible, but the BCLK hardware speed limit means you could only do with at 24 kHz sample rate (if such a large frame really works at all).

    But it might be possible to use 2 parallel TDM frames of 512 bits (on the first port only - SAI2 only supports 1 transmit and 1 receive data pin), if more of the bits in I2S2_TCR3 and I2S2_RCR3 are set. Again, that's guesswork. It definitely does work with I2S protocol, so odds are good that would give 2 TDM streams like we get with quad (2 strereo) I2S. Together with a 512 bit frame size, you could potentially get 3 transmit pins and 3 receive pins with that 512 bit frame by using both SAI1 (2 data pins) & SAI2 (1 data pin).

    What hardware you would connect is a mystery to me. All the TDM chips I've see expect at most a 256 bit frame. That's the reason we support a fixed 256 bit frame with the TDM code in the audio library (and on Teensy 3.x the BCLK spec is 12.5 MHz max). But maybe chips supporting larger frames exist? Or maybe you're planning to roll your own with a FPGA?
    Thank you very much for the help Paul. I am using a max98374, even if the Teensy would be able to handle 32 bit on all 32 channels the Maxim wouldnt be able to handle it. But thanks anyways for helping me out and the detailed answer

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