I don't have any way to test this myself or I would check for you, but based on output_i2s_quad.cpp in the begin function (besides the corresponding pin configs) the parts in red are probably where you would set it up.
Code:
//from imxrt.h
#define I2S_TCR3_TCE_2CH ((uint32_t)0x30000)
Code:
#elif defined(__IMXRT1062__)
const int pinoffset = 0; // TODO: make this configurable...
memset(i2s_tx_buffer, 0, sizeof(i2s_tx_buffer));
AudioOutputI2S::config_i2s();
I2S1_TCR3 = I2S_TCR3_TCE_2CH << pinoffset;
switch (pinoffset) {
case 0:
CORE_PIN7_CONFIG = 3;
CORE_PIN32_CONFIG = 3;
break;
case 1:
CORE_PIN32_CONFIG = 3;
CORE_PIN9_CONFIG = 3;
break;
case 2:
CORE_PIN9_CONFIG = 3;
CORE_PIN6_CONFIG = 3;
}
dma.TCD->SADDR = i2s_tx_buffer;
dma.TCD->SOFF = 2;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DSIZE(1);
dma.TCD->NBYTES_MLOFFYES = DMA_TCD_NBYTES_DMLOE |
DMA_TCD_NBYTES_MLOFFYES_MLOFF(-8) |
DMA_TCD_NBYTES_MLOFFYES_NBYTES(4);
dma.TCD->SLAST = -sizeof(i2s_tx_buffer);
dma.TCD->DADDR = (void *)((uint32_t)&I2S1_TDR0 + 2 + pinoffset * 4);
dma.TCD->DOFF = 4;
dma.TCD->CITER_ELINKNO = AUDIO_BLOCK_SAMPLES * 2;
dma.TCD->DLASTSGA = -8;
dma.TCD->BITER_ELINKNO = AUDIO_BLOCK_SAMPLES * 2;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_SAI1_TX);
dma.enable();
I2S1_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE;
I2S1_TCSR = I2S_TCSR_TE | I2S_TCSR_BCE | I2S_TCSR_FRDE;
I2S1_TCR3 = I2S_TCR3_TCE_2CH << pinoffset;
update_responsibility = update_setup();
dma.attachInterrupt(isr);
#endif
Bits 16-19 each correspond to one tx channel, ie bit 16 is Out1A bit 18 is Out1C, so what I would try is setting I2S1_TCR3 equal to ((uint32_t)0x50000) in the two red places and make sure you have the right configs for pins 7 and 9.