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Thread: D cache management on Teensy4.0

  1. #1

    D cache management on Teensy4.0

    Hello,

    Is there a way to declare a part of the RAM as non cacheable?
    My app has a large data set (500KB) in flash, marked as PROGMEM.

    At this point in time, I am assuming that access to that dataset means that it will be copy in the Dcache..
    However, since I scan said dataset linearly, this will just trash the data cache, but not help as the data is used just once per scan.
    Hence, I would like it NOT to be cached.
    On systems with MMU, one can specify which part of the memory needs to be in the various caches (in 4KB blocks)... but I am not sure that there is a MMU here since this is a cortex M.

    Similarly, they are some parts of the RAM that I would like to not see in the cache (the screen memory to be exact).

    Is there any way to configure the cache with that type of granularity?

    Thanks,
    Cyrille

  2. #2
    Hello,

    looking at the ARM doc, I managed to look at the MPU map for the Teensy 4.0 and found the bellow...

    does anyone know why there are 32 bytes at 0x2000f2c0 with a special setting?

    Cyrille

    startup rom? special for first 32 bytes
    r:0 @0x00000000 exec perm:Priv:NO /prv:No memaccess:Strong order noshared subreg:0 size:0 enabled
    r:1 @0x00000000 noexec perm:Priv:RW /prv:RW memaccess:norm no cache noshared subreg:0 size:512K enabled
    r:2 @0x00000000 noexec perm:Priv:NO /prv:No memaccess:devicereserved noshared subreg:0 size:32 enabled

    ROMCP
    r:3 @0x00200000 noexec perm:Priv:RO /prv:Ro memaccess:Norm write through noshared subreg:0 size:128K enabled

    512K DTCM
    r:4 @0x20000000 exec perm:Priv:RW /prv:RW memaccess:norm no cache noshared subreg:0 size:512K enabled

    Why 32 bytes here?
    r:5 @0x2000f2c0 exec perm:Priv:NO /prv:No memaccess:Strong order noshared subreg:0 size:32 enabled

    1MB OCRam
    r:6 @0x20200000 exec perm:Priv:RW /prv:RW memaccess:norm: write back, write/read allocate noshared subreg:0 size:1M enabled

    HW registers
    r:7 @0x40000000 exec perm:Priv:RW /prv:RW memaccess:devicereserved noshared subreg:0 size:64M enabled

    Flex SPI
    r:8 @0x60000000 noexec perm:Priv:RO /prv:Ro memaccess:norm: write back, write/read allocate noshared subreg:0 size:16M enabled

    Flex SPI 2
    r:9 @0x70000000 exec perm:Priv:RO /prv:Ro memaccess:norm: write back, write/read allocate noshared subreg:0 size:256M enabled
    r:10@0x70000000 exec perm:Priv:RW /prv:RW memaccess:norm: write back, write/read allocate noshared subreg:0 size:16M enabled

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