What is the purpose of these NOPs in Teensy 4.0 initialization?

[ardnew]

In Teensyduino's cores/teensy4/startup.c, the reset ISR void ResetHandler(void) has the following surprise:

     ...

     configure_cache();
     configure_systick();
     usb_pll_start();
     reset_PFD(); //TODO: is this really needed?
 #ifdef F_CPU
     set_arm_clock(F_CPU);
 #endif

     asm volatile("nop\n nop\n nop\n nop": : :"memory"); // why oh why?

     // Undo PIT timer usage by ROM startup
     CCM_CCGR1 |= CCM_CCGR1_PIT(CCM_CCGR_ON);
     PIT_MCR = 0;
     PIT_TCTRL0 = 0;
     PIT_TCTRL1 = 0;
     PIT_TCTRL2 = 0;
     PIT_TCTRL3 = 0;

     ...

It occurs immediately after setting the ARM PLL and core frequencies.

I'm curious what its purpose is, what problem is it alleviating, and if other software reset handlers need to mimic this to avoid a known pitfall?

[MarkT]

Probably to clear the instruction pipeline while the clocks are stabilizing?

[KurtE]

From the comment, because it made it work...

Probably trial and error. MarkT's answer if probably a good guess.

[Pilot]

The operations are there to allow the processor to pause and consider the existential dread it becomes aware of each time it's powered on.

[beermat]

It's a quick snack for the processor. Or is that asm volatile("nom nom nom nom nom")? I forget.

I (and others) use them for short delays; for instance, I'm driving a parallel ILI9488, and strobing the write pin low then high happens too fast for the ILI9488 to read the data @600Mhz T4.1. 8 nops between the low and high provides an appropriate pause.