All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection
to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at
the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|.
Can someone help me understand what this is saying in more basic terms?
Does this mean that if I have some schottky clamping diodes on an I/O to keep in within the rails +- 0.3 V, then I can get away without using a current limiting resistor, even if it's set to output and HIGH?