Just a quick update on my uSDHC / UHS-I / SDR104 findings. People over on the NXP forums have in fact run these iMXRT106x chips successfully at full UHS-1 specifications. There is a register that needs to be flipped that handles the voltage change from 3.3V to 1.8V.
Some of my chicken scratch notes from the iMXRT1060 manual outlining the process:
Code:
26.6.4 Switch Function
A switch command shall be issued by the Host Driver to enable new features added to the
SD/MMC spec. SD/MMC cards can transfer data at bus widths other than 1-bit. Different
speed mode are also defined. To enable these features, a switch command shall be issued
by the Host Driver.
For SDIO cards, the high speed mode/DDR50/SDR50/SDR104 are enabled by writing
the EHS bit in the CCCR register after the SHS bit is confirmed. For SD cards, the high
speed mode/DDR50/SDR50/SDR104 are queried and enabled by a CMD6 (with the
mnemonic symbol as SWITCH_FUNC). For MMC cards , the high speed mode/HS200
are queried by a CMD8 and enabled by a CMD6 (with the mnemonic symbol as
SWITCH).
The SDR4-bit, SDR8-bit ,DDR4-bit and DDR8-bit width of the MMC is also enabled by
the SWITCH command, but with a different argument.
Initialization/Application of uSDHC
i.MX RT1060 Processor Reference Manual, Rev. 2, 12/2019
1538 NXP Semiconduct
Code:
26.6.4.2 Query, Enable and Disable SD High Speed Mode/SDR50/
SDR104/DDR50
enable_sd_speed_mode(void)
{
set BLKCNT field to 1 (block), set BLKSIZE field to 64 (bytes);
send CMD6, with argument 0xFFFFFx and read 64 bytes of data accompanying the R1 response;
(high speed mode,x=1; SDR50,x=2; SDR104,x=3; DDR50,x=4;)
wait data transfer done bit is set;
check if the bit x of received 512 bits is set;
if (bit 401 is '0') report the SD card does not support high speed mode and return;
if (bit 402 is '0') report the SD card does not support SDR50 mode and return;
if (bit 403 is '0') report the SD card does not support SDR104 mode and return;
if (bit 404 is '0') report the SD card does not support DDR50 mode and return;
send CMD6, with argument 0x80FFFFFx and read 64 bytes of data accompanying the R1 response;
(high speed mode,x=1; SDR50,x=2; SDR104 x=3; DDR50 x=4;)
check if the bit field 379~376 is 0xF;
if (the bit field is 0xF) report the function switch failed and return;
change clock divisor value or configure the system clock feeding into uSDHC to generate the
card_clk of around 50MHz for high speed mode, 100Mhz for SDR50, 200Mhz for SDR104, 50Mhz for
DDR50;
(data transactions like normal peers)
}
disable_sd_speed_mode(void)
{
set BLKCNT field to 1 (block), set BLKSIZE field to 64 (bytes);
send CMD6, with argument 0x80FFFFF0 and read 64 bytes of data accompanying the R1 response;
check if the bit field 379~376 is 0xF;
Chapter 26 Ultra Secured Digital Host Controller (uSDHC)
i.MX RT1060 Processor Reference Manual, Rev. 2, 12/2019
NXP Semiconductors 1539
if (the bit field is 0xF) report the function switch failed and return;
change clock divisor value or configure the system clock feeding into uSDHC to generate the
card_clk of the desired value below 25MHz;
(data transactions like normal peers)
}
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Originally Posted by LitterBug
