Forum Rule: Always post complete source code & details to reproduce any issue!
Page 3 of 3 FirstFirst 1 2 3
Results 51 to 66 of 66

Thread: Teensyduino 1.54 Beta #4

  1. #51
    Senior Member+ KurtE's Avatar
    Join Date
    Jan 2014
    Posts
    7,912
    Here is a longer one:
    Code:
    OV7670 Camera Test 3  Compiled on Nov 15 2020 05:31:56
    EXT Memory size: 8
    Read Register(Write): 11 error: 2
    I2C Write: reg: 0x11(CLKRC), value = 0x41
    I2C Write: reg: 0x6b(DBLV), value = 0x4a
    cam clock  12.00 with pll=1 and div=1
    ...
    I2C Write: reg: 0x19(VSTART), value = 0x01
    I2C Write: reg: 0x1a(VSTOP), value = 0x79
    I2C Write: reg: 0x03(VREF), value = 0x3f
    ::begin 0 255 255 255
    ILI9488_t3::begin - End
    After cameraBegin(end setup)
    s - Show Information
    c - Print CSI Registers
    r - Show Camera registers
    f - Show a frame
    x - Send Raw (Processing Sketch)
    d - Save Image to SD Card
    t - send Image to ILI9341
    v - Send continuous images to ILI9341
    Command character received: c
    ==== CSI ====
    CSI_CSICR1: 401B0912
    CSI_CSICR2: C0000000
    CSI_CSICR3: 33C1020
    CSI_CSISTATFIFO: 0
    CSI_CSIRFIFO: 630E5AEE
    CSI_CSIRXCNT: 9600
    CSI_CSISR: 84204001
    CSI_CSIDMASA_STATFIFO: 0
    CSI_CSIDMATS_STATFIFO: 0
    CSI_CSIDMASA_FB1: 70000000
    CSI_CSIDMASA_FB2: 70096000
    CSI_CSIFBUF_PARA: 0
    CSI_CSIIMAG_PARA: 50001E0
    CSI_CSICR18: 800AD210
    CSI_CSICR19: 10
    CSI_CSIRFIFO: 73907390
    Command character received: 
    Command character received: 
    
    Command character received: r
    00(GAIN):FE
    01(BLUE):58
    02(RED):40
    03(VREF):FF
    04(COM1):01
    05(BAVE):7F
    06(GbAVE):87
    07(AECHH):40
    08(RAVE):87
    09(COM2):01
    0A(PID):76
    0B(VER):73
    0C(COM3):00
    0D(COM4):40
    0E(COM5):61
    0F(COM6):4B
    10(AECH):7F
    11(CLKRC):80
    12(COM7):04
    13(COM8):C7
    14(COM9):6A
    15(COM10):22
    16(*RSVD*):02
    17(HSTART):16
    18(HSTOP):04
    19(VSTART):01
    1A(VSTOP):79
    1B(PSHFT):00
    1C(MIDH):7F
    1D(MIDL):A2
    1E(MVFP):07
    1F(LAEC):00
    20(ADCCTR0):04
    21(ADCCTR1):02
    22(ADCCTR2):91
    23(ADCCTR3):00
    24(AEW):95
    25(AEB):33
    26(VPT):E3
    27(BBIAS):80
    28(GbBIAS):80
    29(*RSVD*):07
    2A(EXHCH):00
    2B(EXHCL):00
    2C(RBIAS):80
    2D(ADVFL):00
    2E(ADVFH):00
    2F(YAVE):3E
    30(HSYST):00
    31(HSYEN):00
    32(HREF):B6
    33(CHLF):0B
    34(ARBLM):11
    35(*RSVD*):0B
    36(*RSVD*):00
    37(ADC):1D
    38(ACOM):71
    39(OFON):2A
    3A(TSLB):0D
    3B(COM11):12
    3C(COM12):78
    3D(COM13):40
    3E(COM14):18
    3F(EDGE):00
    40(COM15):D0
    41(COM16):08
    42(COM17):00
    43(AWBC1):0A
    44(AWBC2):F0
    45(AWBC3):34
    46(AWBC4):58
    47(AWBC5):28
    48(AWBC6):3A
    49(*RSVD*):00
    4A(*RSVD*):00
    4B(REG4B):09
    4C(DNSTH):00
    4D(DM_POS):40
    4E(*RSVD*):20
    4F(MTX1):B3
    50(MTX2):B3
    51(MTX3):00
    52(MTX4):3D
    53(MTX5):A7
    54(MTX6):E4
    55(BRIGHT):32
    56(CONTRAS):5C
    57(CONTRAS_CENTER):80
    58(MTXS):9E
    59(AWBC7):88
    5A(AWBC8):88
    5B(AWBC9):44
    5C(AWBC10):67
    5D(AWBC11):49
    5E(AWBC12):0E
    5F(B_LMT):F0
    60(R_LMT):F0
    61(G_LMT):F0
    62(LCC1):00
    63(LCC2):00
    64(LCC3):50
    65(LCC4):30
    66(LCC5):00
    67(MANU):80
    68(MANV):80
    69(GFIX):00
    6A(GGAIN):40
    6B(DBLV):0A
    6C(AWBCTR3):0A
    6D(AWBCTR2):55
    6E(AWBCTR1):11
    6F(AWBCTR0):9E
    70(SCALING_XSC):3A
    71(SCALING_YSC):35
    72(SCALING_DCWCTR):00
    73(SCALING_PCLK_DIV):F0
    74(REG74):10
    75(REG75):05
    76(REG76):E1
    77(REG77):01
    78(*RSVD*):04
    79(*RSVD*):26
    7A(SLOP):20
    7B(GAMA1):10
    7C(GAMA2):1E
    7D(GAMA3):35
    7E(GAMA4):5A
    7F(GAMA5):69
    80(GAMA6):76
    81(GAMA7):80
    82(GAMA8):88
    83(GAMA9):8F
    84(GAMA10):96
    85(GAMA11):A3
    86(GAMA12):AF
    87(GAMA13):C4
    88(GAMA14):D7
    89(GAMA15):E8
    8A(*RSVD*):00
    8B(*RSVD*):00
    8C(?RGB444):00
    8D(*RSVD*):4F
    8E(*RSVD*):00
    8F(*RSVD*):00
    90(*RSVD*):00
    91(*RSVD*):00
    92(DM_LNL):00
    93(DM_LNH):00
    94(LCC6):50
    95(LCC7):50
    96(*RSVD*):00
    97(*RSVD*):30
    98(*RSVD*):20
    99(*RSVD*):30
    9A(*RSVD*):84
    9B(*RSVD*):29
    9C(*RSVD*):03
    9D(BD50ST):4C
    9E(BD60ST):3F
    9F(HAECC1):78
    A0(HAECC2):68
    A1(DSPC3):03
    A2(SCALING_PCLK_DELAY):01
    A3(*RSVD*):01
    A4(NT_CTRL):82
    A5(AECGMAX):05
    A6(LPH):D8
    A7(UPL):D8
    A8(TPL):F0
    A9(TPH):90
    AA(NALG):94
    AB(*RSVD*):07
    AC(STR-OPT):00
    AD(STR_R):80
    AE(STR_G):80
    AF(STR_B):80
    B0(*RSVD*):84
    B1(ABLC1):0C
    B2(*RSVD*):0E
    B3(THL_ST):82
    B4(*RSVD*):00
    B5(THL_DLT):04
    B6(*RSVD*):00
    B7(*RSVD*):66
    B8(*RSVD*):0A
    B9(*RSVD*):06
    BA(*RSVD*):00
    BB(*RSVD*):00
    BC(*RSVD*):00
    BD(*RSVD*):00
    BE(AD-CHB):27
    BF(AD-CHR):20
    C0(AD-CHGb):39
    C1(AD-CHRr):35
    C2(*RSVD*):00
    C3(*RSVD*):00
    C4(*RSVD*):00
    C5(*RSVD*):00
    C6(*RSVD*):00
    C7(*RSVD*):00
    C8(*RSVD*):A0
    C9(SATCTR):67
    Command character received: 
    Command character received:
    From this test which has combination of print, println, printf, looks like it is working!

  2. #52
    Member LitterBug's Avatar
    Join Date
    Nov 2020
    Location
    Earth
    Posts
    24
    Just a quick update on my uSDHC / UHS-I / SDR104 findings. People over on the NXP forums have in fact run these iMXRT106x chips successfully at full UHS-1 specifications. There is a register that needs to be flipped that handles the voltage change from 3.3V to 1.8V.

    Some of my chicken scratch notes from the iMXRT1060 manual outlining the process:
    Code:
    26.6.4 Switch Function
    A switch command shall be issued by the Host Driver to enable new features added to the
    SD/MMC spec. SD/MMC cards can transfer data at bus widths other than 1-bit. Different
    speed mode are also defined. To enable these features, a switch command shall be issued
    by the Host Driver.
    For SDIO cards, the high speed mode/DDR50/SDR50/SDR104 are enabled by writing
    the EHS bit in the CCCR register after the SHS bit is confirmed. For SD cards, the high
    speed mode/DDR50/SDR50/SDR104 are queried and enabled by a CMD6 (with the
    mnemonic symbol as SWITCH_FUNC). For MMC cards , the high speed mode/HS200
    are queried by a CMD8 and enabled by a CMD6 (with the mnemonic symbol as
    SWITCH).
    The SDR4-bit, SDR8-bit ,DDR4-bit and DDR8-bit width of the MMC is also enabled by
    the SWITCH command, but with a different argument.
    Initialization/Application of uSDHC
    i.MX RT1060 Processor Reference Manual, Rev. 2, 12/2019
    1538 NXP Semiconduct
    Code:
    26.6.4.2 Query, Enable and Disable SD High Speed Mode/SDR50/
    SDR104/DDR50
    enable_sd_speed_mode(void)
    {
    set BLKCNT field to 1 (block), set BLKSIZE field to 64 (bytes);
    send CMD6, with argument 0xFFFFFx and read 64 bytes of data accompanying the R1 response;
    (high speed mode,x=1; SDR50,x=2; SDR104,x=3; DDR50,x=4;)
    wait data transfer done bit is set;
    check if the bit x of received 512 bits is set;
    if (bit 401 is '0') report the SD card does not support high speed mode and return;
    if (bit 402 is '0') report the SD card does not support SDR50 mode and return;
    if (bit 403 is '0') report the SD card does not support SDR104 mode and return;
    if (bit 404 is '0') report the SD card does not support DDR50 mode and return;
    send CMD6, with argument 0x80FFFFFx and read 64 bytes of data accompanying the R1 response;
    (high speed mode,x=1; SDR50,x=2; SDR104 x=3; DDR50 x=4;)
    check if the bit field 379~376 is 0xF;
    if (the bit field is 0xF) report the function switch failed and return;
    change clock divisor value or configure the system clock feeding into uSDHC to generate the
    card_clk of around 50MHz for high speed mode, 100Mhz for SDR50, 200Mhz for SDR104, 50Mhz for
    DDR50;
    (data transactions like normal peers)
    }
    disable_sd_speed_mode(void)
    {
    set BLKCNT field to 1 (block), set BLKSIZE field to 64 (bytes);
    send CMD6, with argument 0x80FFFFF0 and read 64 bytes of data accompanying the R1 response;
    check if the bit field 379~376 is 0xF;
    Chapter 26 Ultra Secured Digital Host Controller (uSDHC)
    i.MX RT1060 Processor Reference Manual, Rev. 2, 12/2019
    NXP Semiconductors 1539
    if (the bit field is 0xF) report the function switch failed and return;
    change clock divisor value or configure the system clock feeding into uSDHC to generate the
    card_clk of the desired value below 25MHz;
    (data transactions like normal peers)
    }

  3. #53
    Senior Member vjmuzik's Avatar
    Join Date
    Apr 2017
    Posts
    688
    Quote Originally Posted by LitterBug View Post
    Just a quick update on my uSDHC / UHS-I / SDR104 findings. People over on the NXP forums have in fact run these iMXRT106x chips successfully at full UHS-1 specifications. There is a register that needs to be flipped that handles the voltage change from 3.3V to 1.8V.

    Some of my chicken scratch notes from the iMXRT1060 manual outlining the process:
    Code:
    26.6.4 Switch Function
    A switch command shall be issued by the Host Driver to enable new features added to the
    SD/MMC spec. SD/MMC cards can transfer data at bus widths other than 1-bit. Different
    speed mode are also defined. To enable these features, a switch command shall be issued
    by the Host Driver.
    For SDIO cards, the high speed mode/DDR50/SDR50/SDR104 are enabled by writing
    the EHS bit in the CCCR register after the SHS bit is confirmed. For SD cards, the high
    speed mode/DDR50/SDR50/SDR104 are queried and enabled by a CMD6 (with the
    mnemonic symbol as SWITCH_FUNC). For MMC cards , the high speed mode/HS200
    are queried by a CMD8 and enabled by a CMD6 (with the mnemonic symbol as
    SWITCH).
    The SDR4-bit, SDR8-bit ,DDR4-bit and DDR8-bit width of the MMC is also enabled by
    the SWITCH command, but with a different argument.
    Initialization/Application of uSDHC
    i.MX RT1060 Processor Reference Manual, Rev. 2, 12/2019
    1538 NXP Semiconduct
    Code:
    26.6.4.2 Query, Enable and Disable SD High Speed Mode/SDR50/
    SDR104/DDR50
    enable_sd_speed_mode(void)
    {
    set BLKCNT field to 1 (block), set BLKSIZE field to 64 (bytes);
    send CMD6, with argument 0xFFFFFx and read 64 bytes of data accompanying the R1 response;
    (high speed mode,x=1; SDR50,x=2; SDR104,x=3; DDR50,x=4;)
    wait data transfer done bit is set;
    check if the bit x of received 512 bits is set;
    if (bit 401 is '0') report the SD card does not support high speed mode and return;
    if (bit 402 is '0') report the SD card does not support SDR50 mode and return;
    if (bit 403 is '0') report the SD card does not support SDR104 mode and return;
    if (bit 404 is '0') report the SD card does not support DDR50 mode and return;
    send CMD6, with argument 0x80FFFFFx and read 64 bytes of data accompanying the R1 response;
    (high speed mode,x=1; SDR50,x=2; SDR104 x=3; DDR50 x=4;)
    check if the bit field 379~376 is 0xF;
    if (the bit field is 0xF) report the function switch failed and return;
    change clock divisor value or configure the system clock feeding into uSDHC to generate the
    card_clk of around 50MHz for high speed mode, 100Mhz for SDR50, 200Mhz for SDR104, 50Mhz for
    DDR50;
    (data transactions like normal peers)
    }
    disable_sd_speed_mode(void)
    {
    set BLKCNT field to 1 (block), set BLKSIZE field to 64 (bytes);
    send CMD6, with argument 0x80FFFFF0 and read 64 bytes of data accompanying the R1 response;
    check if the bit field 379~376 is 0xF;
    Chapter 26 Ultra Secured Digital Host Controller (uSDHC)
    i.MX RT1060 Processor Reference Manual, Rev. 2, 12/2019
    NXP Semiconductors 1539
    if (the bit field is 0xF) report the function switch failed and return;
    change clock divisor value or configure the system clock feeding into uSDHC to generate the
    card_clk of the desired value below 25MHz;
    (data transactions like normal peers)
    }
    I'm pretty sure I remember talks of this before and the problem had to do with it being hardwired at 3.3v and the pin that is supposed to make the change to 1.8v wasn't exposed anywhere.

  4. #54
    Member LitterBug's Avatar
    Join Date
    Nov 2020
    Location
    Earth
    Posts
    24
    Quote Originally Posted by vjmuzik View Post
    I'm pretty sure I remember talks of this before and the problem had to do with it being hardwired at 3.3v and the pin that is supposed to make the change to 1.8v wasn't exposed anywhere.
    It is handled internal to the CPU. no external hardware is necissary.

  5. #55
    Senior Member vjmuzik's Avatar
    Join Date
    Apr 2017
    Posts
    688
    I thought the SD card needs to be powered from 1.8v as well, it is currently hardwired to 3.3v with no way to change it and from what I remember there was a pin on the processor that would toggle when it is is supposed to go into 1.8v mode so that you can change the voltage of the SD card using that signal.

  6. #56
    Member LitterBug's Avatar
    Join Date
    Nov 2020
    Location
    Earth
    Posts
    24
    Quote Originally Posted by vjmuzik View Post
    I thought the SD card needs to be powered from 1.8v as well, it is currently hardwired to 3.3v with no way to change it and from what I remember there was a pin on the processor that would toggle when it is is supposed to go into 1.8v mode so that you can change the voltage of the SD card using that signal.
    The NXP reference board has the SD VDD wired the same to 3.3v, and pretty much the rest of the SD slot for that matter. No level shifter between the CPU and SDcard.
    Click image for larger version. 

Name:	uSDHC1schem1.png 
Views:	8 
Size:	53.5 KB 
ID:	22565
    Click image for larger version. 

Name:	uSDHC1schem.png 
Views:	9 
Size:	62.3 KB 
ID:	22564

    The SDCARD SDIO reference says the supply voltage should be 2.7-3.6V
    The "signaling voltage" needs to switch to 1.8V for the SDR### modes, not the Supply voltage.

    LB

    EDIT: The hidden signal: SD0_VSELECT is an internal register for the internal IOMUXC. It would not show up on an external pin....
    Last edited by LitterBug; 11-22-2020 at 02:49 AM.

  7. #57
    Senior Member vjmuzik's Avatar
    Join Date
    Apr 2017
    Posts
    688
    I see now it's not the SD cards power that needs to change it's the NVCC_SD voltage that has to change, which based on the Teensy 4 schematic is hardwired to 3.3v so currently we can't do anything about that. As per the data sheet the signaling voltage is derived from NVCC_SD which has to be 1.8v to use SDR104/SDR50 speeds.

  8. #58
    Senior Member vjmuzik's Avatar
    Join Date
    Apr 2017
    Posts
    688
    The pins for VSELECT can be found in the reference manual, which does show the external pins that it maps to, for SD0 it can be one of these 4 pins here:
    Code:
    USDHC1_VSELECT
    GPIO_EMC_41 ALT6
    GPIO_AD_B1_01 ALT6
    GPIO_B1_14 ALT6
    GPIO_EMC_34 ALT2

  9. #59
    Member LitterBug's Avatar
    Join Date
    Nov 2020
    Location
    Earth
    Posts
    24
    Those are internal pins on the IOMUXC. Not exposed pins. The voltage selection and change happens inside the CPU via a configuration register.

    Click image for larger version. 

Name:	IOmuxSD-MMC.png 
Views:	5 
Size:	47.1 KB 
ID:	22567
    Last edited by LitterBug; 11-22-2020 at 04:06 AM.

  10. #60
    Senior Member vjmuzik's Avatar
    Join Date
    Apr 2017
    Posts
    688
    They are very much exposed pins and not just internal though the only one we have exposed is AD_B1_01 which is pin 18 on the Teensy 4.1. Like I said earlier that pin would be responsible for changing the voltage going in to NVCC_SD to 1.8v by triggering external circuitry. But since it’s hardwired and there is no hardware in place it can’t currently be done.

  11. #61
    Member LitterBug's Avatar
    Join Date
    Nov 2020
    Location
    Earth
    Posts
    24
    The IOMUX is an internal component of the CPU. it is NOT exposed. VSELECT gets set by writing to CMD6. The IOMUX does the the voltage change internally.
    Code:
    For SDIO cards, the high speed mode/DDR50/SDR50/SDR104 are enabled by writing
    the EHS bit in the CCCR register after the SHS bit is confirmed. For SD cards, the high
    speed mode/DDR50/SDR50/SDR104 are queried and enabled by a CMD6 (with the
    mnemonic symbol as SWITCH_FUNC).
    This all happens inside the CPU and does not require any additional hardware. You are making it harder than it is.

  12. #62
    Senior Member vjmuzik's Avatar
    Join Date
    Apr 2017
    Posts
    688
    It's not rocket science, the reference manual tells you you need external circuitry, so you need external circuitry:
    Click image for larger version. 

Name:	Screen Shot 2020-11-21 at 11.40.44 PM.jpg 
Views:	11 
Size:	39.4 KB 
ID:	22568

  13. #63
    Member LitterBug's Avatar
    Join Date
    Nov 2020
    Location
    Earth
    Posts
    24
    Quote Originally Posted by vjmuzik View Post
    It's not rocket science, the reference manual tells you you need external circuitry, so you need external circuitry:
    Click image for larger version. 

Name:	Screen Shot 2020-11-21 at 11.40.44 PM.jpg 
Views:	11 
Size:	39.4 KB 
ID:	22568
    Which is an internal signal handled by the IOMUX.

  14. #64
    Senior Member vjmuzik's Avatar
    Join Date
    Apr 2017
    Posts
    688
    The IOMUX is responsible for routing internal registers to external signals, just turning on VSELECT will not change to 1.8v mode. VSELECT for SD0 can be routed to one of four pins through the IOMUX, you then need external circuitry on that pin that changes NVCC_SD from 3.3v to 1.8v.

  15. #65
    Member LitterBug's Avatar
    Join Date
    Nov 2020
    Location
    Earth
    Posts
    24
    I think I see the error in my ways after a lot more digging.

    I think there is an easy workaround whether or not the vselect signal is output on the intended pin or not. There is nothing stopping someone from using a different pin for VSELECT in the SDIO/SDFat routines. The Teensy 4.0 does not have a SDcard holder mounted by default. Should be easy enough to set up a level shifter. The 4.1 would need to have the card holder removed or if you are good at soldering, you may be able to get wires on the pads with the existing holder in place. I have also seen microSD card breakouts.
    Click image for larger version. 

Name:	SDbreakout.jpg 
Views:	4 
Size:	73.7 KB 
ID:	22569

    The logic is still needed in SDIO/SDFat for checking the card for it's capabilities, setting whatever VSELECT pin is used in addition to setting the CMD6 register, and then setting the clocking.

    LB
    Last edited by LitterBug; 11-22-2020 at 06:27 AM.

  16. #66
    Member LitterBug's Avatar
    Join Date
    Nov 2020
    Location
    Earth
    Posts
    24
    Sorry if I was a little thick headed, but I have seen the light.

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •