TO SUM UP: i managed to latch each pin to his gpio port, yet some of those still refuses to cooperate. I think alternate functions is responsable for this. IOMUXC is a mess (?).
I am close. Thanks to core_pins.h i finally found out that i can address to the registers using for example GPIO3_DR, and so on for all of the GPIOs. Here is a list of all gpio with the latched pins:
Code:
GPIO6 ---> 0, 1, 14 to 27
GPIO7 ---> 6 to 13, 32
GPIO8 ---> 28 to 31, 34 to 39
GPIO9---> 2 to 5, 29 to 33
for reference, here's the original code
/ Fast GPIO
#define CORE_PIN0_PORTREG GPIO6_DR
#define CORE_PIN1_PORTREG GPIO6_DR
#define CORE_PIN2_PORTREG GPIO9_DR
#define CORE_PIN3_PORTREG GPIO9_DR
#define CORE_PIN4_PORTREG GPIO9_DR
#define CORE_PIN5_PORTREG GPIO9_DR
#define CORE_PIN6_PORTREG GPIO7_DR
#define CORE_PIN7_PORTREG GPIO7_DR
#define CORE_PIN8_PORTREG GPIO7_DR
#define CORE_PIN9_PORTREG GPIO7_DR
#define CORE_PIN10_PORTREG GPIO7_DR
#define CORE_PIN11_PORTREG GPIO7_DR
#define CORE_PIN12_PORTREG GPIO7_DR
#define CORE_PIN13_PORTREG GPIO7_DR
#define CORE_PIN14_PORTREG GPIO6_DR
#define CORE_PIN15_PORTREG GPIO6_DR
#define CORE_PIN16_PORTREG GPIO6_DR
#define CORE_PIN17_PORTREG GPIO6_DR
#define CORE_PIN18_PORTREG GPIO6_DR
#define CORE_PIN19_PORTREG GPIO6_DR
#define CORE_PIN20_PORTREG GPIO6_DR
#define CORE_PIN21_PORTREG GPIO6_DR
#define CORE_PIN22_PORTREG GPIO6_DR
#define CORE_PIN23_PORTREG GPIO6_DR
#define CORE_PIN24_PORTREG GPIO6_DR
#define CORE_PIN25_PORTREG GPIO6_DR
#define CORE_PIN26_PORTREG GPIO6_DR
#define CORE_PIN27_PORTREG GPIO6_DR
#define CORE_PIN28_PORTREG GPIO8_DR
#define CORE_PIN29_PORTREG GPIO9_DR
#define CORE_PIN30_PORTREG GPIO8_DR
#define CORE_PIN31_PORTREG GPIO8_DR
#define CORE_PIN32_PORTREG GPIO7_DR
#define CORE_PIN33_PORTREG GPIO9_DR
#define CORE_PIN34_PORTREG GPIO8_DR
#define CORE_PIN35_PORTREG GPIO8_DR
#define CORE_PIN36_PORTREG GPIO8_DR
#define CORE_PIN37_PORTREG GPIO8_DR
#define CORE_PIN38_PORTREG GPIO8_DR
#define CORE_PIN39_PORTREG GPIO8_DR
Now, i tried again the toggling code just to be sure, and some pins (a lot of them actually) are still not responding. This led me to think that some alternate function register was preventing those pins to be used as GPIO. So here comes the IOMUX control register. In page 304 there is a list of how gpio are linked to this register, and i find it really confusing. How come there are only GPIO1 to 5? Diving deeper in the IOMUXC specs literally makes me crazy, there are tons and tons of registers (35 actually). So, core_pins.h seems to have a list of defines to take care of those, but i really don't know how to properly use all this informations.
Code:
// mux config registers control which peripheral uses the pin
#define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
#define CORE_PIN1_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
#define CORE_PIN2_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
#define CORE_PIN3_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
#define CORE_PIN4_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
#define CORE_PIN5_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
#define CORE_PIN6_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
#define CORE_PIN7_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
#define CORE_PIN8_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
#define CORE_PIN9_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
#define CORE_PIN10_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
#define CORE_PIN11_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
#define CORE_PIN12_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
#define CORE_PIN13_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
#define CORE_PIN14_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
#define CORE_PIN15_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
#define CORE_PIN16_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
#define CORE_PIN17_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
#define CORE_PIN18_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
#define CORE_PIN19_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
#define CORE_PIN20_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
#define CORE_PIN21_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
#define CORE_PIN22_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
#define CORE_PIN23_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
#define CORE_PIN24_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
#define CORE_PIN25_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
#define CORE_PIN26_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
#define CORE_PIN27_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
#define CORE_PIN28_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
#define CORE_PIN29_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
#define CORE_PIN30_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
#define CORE_PIN31_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
#define CORE_PIN32_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
#define CORE_PIN33_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
#define CORE_PIN34_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
#define CORE_PIN35_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
#define CORE_PIN36_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
#define CORE_PIN37_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
#define CORE_PIN38_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
#define CORE_PIN39_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
for reference, here's the testing code
Code:
int state = 0xFFFF;
void setup() {
GPIO8_GDIR = 0xFFFF;
Serial.begin(9600);
}
void loop() {
state = 0xFFFF - state;
GPIO8_DR = state;
delay(200);
}
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Originally Posted by TRNPep
