Not really.
It just makes sure that the CPU resets as soon as possible. Otherwise it can happen some cycles later. If you want to be on the save side, add the "dsb".
It has to do with very technical details, pipelines and more.. it is a "barrier".
ARM says:
Data
Synchronization
Barrier acts as a special kind of memory barrier. No instruction in program order after this instruction executes until this instruction completes. This instruction completes when:
- All explicit memory accesses before this instruction complete.
- All Cache, Branch predictor and TLB maintenance operations before this instruction complete.
Esp. on Teensy4, (ARM Cortex-M7) a DSB is mandatory at the end of interrupt-code. Without, it can happen, that a interrupt gets called twice, because the corresponding flags have not been written early enough.
The Reset is more or less the same.. without "DSB" it
will happen, but you can not predict
when exactly.
ARM suggests the following code for a reset:
Code:
SCB_AIRCR = 0x05FA0004;
asm volatile ("dsb");
while (1) {;}
For these reasons:
1) It helps to compiler to detect that this code never returns and can optimize the calling code better. It does not know that SCB_AIRCR = 0x05FA0004 means "reset".
2) It makes sure that no "digitalWriteFast(Flamethrower_enable_PIN, HIGH)" happens...
3) ... ?