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Thread: Teensy 4.1 - clock output capability for high speed ADC

  1. #1
    Junior Member
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    Teensy 4.1 - clock output capability for high speed ADC

    I was looking at using a NXP i.MX RT1060 series microcontroller for a project when I learned of the Teensy 4.1. I'd like to use the Teensy for prototyping a high-speed data collection device. For this, I would like to use the Teensy 4.1 to generate a clock signal for a MAX1448 ADC at 80 MHz. The ADC will generate a 10-bit digital output in parallel format for each clock cycle (80 MHz frequency, 50% duty cycle). I know the MCU itself has clock out capability via the CCM, but it looks like those pins aren't available on the Teensy 4.1.

    Is there another option for generating a clean output clock for a high-speed ADC?

  2. #2
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    Quote Originally Posted by landshark42 View Post
    I was looking at using a NXP i.MX RT1060 series microcontroller for a project when I learned of the Teensy 4.1. I'd like to use the Teensy for prototyping a high-speed data collection device. For this, I would like to use the Teensy 4.1 to generate a clock signal for a MAX1448 ADC at 80 MHz. The ADC will generate a 10-bit digital output in parallel format for each clock cycle (80 MHz frequency, 50% duty cycle). I know the MCU itself has clock out capability via the CCM, but it looks like those pins aren't available on the Teensy 4.1.

    Is there another option for generating a clean output clock for a high-speed ADC?
    You could get 75MHz by setting analogoutfrequency on a PWM-capable pin. I think that's as high as you can go as it is 1/2 the bus frequency of 150MHz. Perhaps you could get 80MHz by overclocking the T4.1, but that might lead to other problems.

    Getting good result with an ADC at that clock and conversion speed is going to require pretty good board layout. Processing 80 million 10-bit samples per second sounds like an interesting problem (along the lines of the ancient Chinese curse: "May you live in interesting times".)

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