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Thread: Pwm

  1. #1
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    Pwm

    I am having a bit of trouble trying to determine what the actual resolution I get on a PWM through analogWrite() is.

    I am on a 4.0 board. My PWM is fixed @ 40kHz, and I have set the resolution to 12b like this:

    analogWriteFrequency(2, 40000);
    analogWriteResolution(12);

    Now, the docs says the optimal frequency for this resolution is 36621.09Hz, which I am above. Does this mean, that my resolution goes down a whole bit?

    Also, does it make any difference whether I use a FlexPWM timer or a QuadTimer? Or if i change the CPU speed? The PWM must be 40kHz, but I need the resolution as high as I can get it.

    Thanks in advance

  2. #2
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by Jolenedk View Post
    Now, the docs says the optimal frequency for this resolution is 36621.09Hz, which I am above. Does this mean, that my resolution goes down a whole bit?
    Yes, but not by a whole bit. The software will linearly map your desired 4096 steps onto the 3750 steps the hardware can provide. So if we think of stepping up in PWM duty cycle 1 number at a time, most of your increments by 1/4096th will actually increment by 1/3750th, and some of them (a few hundred) will not increment at all, giving exactly the same PWM output as the prior step.

    To quickly answer your other questions...


    Also, does it make any difference whether I use a FlexPWM timer or a QuadTimer?
    No.


    Or if i change the CPU speed?
    Yes. Both types of timers run from 1/4 the CPU frequency. At 600 MHz, the timers clock at 150 MHz. 150e6 / 40e3 = 3750 steps.


    The PWM must be 40kHz, but I need the resolution as high as I can get it.
    That's exactly how the software works. You pick a frequency & resolution and the software linearly maps your specified resolution onto the actual resolution the hardware provides at that frequency.

  3. #3
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    Thanks Paul, this was exactly the information I needed.

  4. #4
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    Once again, thank you for a quick reply. I now have everything working at 12 bits resolution.

    My objective here is to get optimal PWM resolution on a 40kHz carrier. I am working with audio, so really the 13-14 bits theoretical max from 600MHz is the goal.

    - Can I change the FlexPWM prescaler to 1 or 2 to get half or full CPU frequency, enabling higher resolution? If so, how (cannot seem to find it, but then again, its late in Denmark...)
    - I am aware the onboard ADC, which I am currently sampling audio from, only gives me 12 theoretical and 10 usable bits. With the audio shield - can I do single-shot reads @ 16b over I2S without having to use 44K1Hz (or any other predefined) samplingrate?

    All the best/Jonas

  5. #5
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    You know how to get twice the bit depth by using two PWM pins? http://www.openmusiclabs.com/learnin...its/index.html

  6. #6
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by Jolenedk View Post
    - Can I change the FlexPWM prescaler to 1 or 2 to get half or full CPU frequency, enabling higher resolution?
    The prescaler already is at 1 (fastest possible) with the settings mentioned.

    FlexPWM and QTimer run from the peripheral clock (called "IPG" clock in the manual), not from the CPU clock. The division by 4 happens in generating the IPG clock from the CPU clock.


    With the audio shield - can I do single-shot reads @ 16b over I2S without having to use 44K1Hz (or any other predefined) samplingrate?
    No, definitely not. Like virtually all audio ADCs, the conversion is done using a technique called delta-sigma modulation. You can search for that phrase to learn how it works (or perhaps find highly theoretical academic papers) but the general concept is a low resolution ADC is run at an incredibly high sample rate. Built into the analog circuitry is the delta sigma modulator which uses an analog integrator in a feedback loop to shift all the low-res error to high frequencies while allowing the input signal to pass unchanged. Then a digital filter discards all the non-audio high frequency data, leaving the only the original signal. Running at a consistent sample rate is a fundamental part of both the modulator and filter. These sorts of audio ADCs are never able to do a single-shot sampling of the signal.

    The ADC built into Teensy which uses a successive approximation approach, which fundamentally a single-shot sampling hardware.


    My objective here is to get optimal PWM resolution on a 40kHz carrier. I am working with audio, so really the 13-14 bits theoretical max from 600MHz is the goal.
    The only way to get higher PWM resolution is to overclock IPG. The simplest way is to just overclock the entire chip, using the Tools > CPU Speed menu. Or you could edit the startup code and configure the whole chip to run at 655.36 MHz, which is just under 10% overclock. Or you could configure for a CPU clock of 491.52 MHz and edit that the clock config code to use divide-by-3 for CPU-to-IPG (it should use div-by-4 for this, since 150 MHz is the rated max for IPG).

    Or if you're using PWM as a "poor man's DAC" for audio, maybe consider using the very cheap PT8211 chip.
    Last edited by PaulStoffregen; 03-06-2021 at 07:45 AM.

  7. #7
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    Thanks, this was most helpful,

    I am transferring audio using ultrasound, but maybe pushing the resolution beyond 12 bits is not feasible here, since it seems to be the limit at both the ADC and PWM end. Maybe I can get an extra bit using the 2 ADCs in sync. Still, I am not sure the physical transfer allows for higher precision either.

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    I somehow fried my 4.0 board, and am now duplicating my test setup to a 3.5 board I had lying around. Good news seems to be better ADC performance, but do the FTO timers for the PWM on the 3.5 board also run at 1/4 system clock, or how does that go?

  9. #9
    Senior Member PaulStoffregen's Avatar
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    On both Teensy 4.0 and 3.5, the timers run from a peripheral clock which is slower than the CPU clock.

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