I was asking about memory prefetches.
There are hint instructions that tell the CPU that an access to a specific memory location is likely in the near future.
PLD for Data, PLI for instructions. The CPU then can instruct the memory interface to do steps that lead to a faster access.
For the cache, it could be a prefetch?
As I learned now, only the instruction cache does automatic prefetch. Is that correct?
SO, i could imagine a speedup for data, for example before loops (i.e. like a memcpy, fast caluclation that read an array etc)
I have no idea how much impact they have, and that's why I ask.
Are they useful? If I look at the audio library, it would be full of use cases.
a side question
in arm_dcache* functions we find
Code:
asm volatile("": : :"memory");
asm("dsb");
if I take disable_irq() we have
Code:
#define __disable_irq() __asm__ volatile("CPSID i":::"memory");
how should we read this?
IOW, could we use
Code:
__asm__ volatile("dsb":::"memory");
or is the order: first "": : :"memory" and then "dsb" , of importance?
:::memory is a hint for the compiler. It tells him to do all load/store instructions before the barrierer, If I'm right.
For the interrupts I can only imagine a few corner cases where this makes sense: When data need to be written _before_ an interrupts occurs. If you write to the vector table, for example.
Are there more cases?