Memory hints

[Frank B]

Has anyone used or tried "memory hints" (assembler commands) and can say if they work and are useful on Teensy 3...4?

 

[defragster]

Like this :: asm volatile("" : : : "memory");

Paul added that to t_4's : delay.c :: uint32_t micros(void)

With that and a conditional - that is about NEVER true - it runs at least 2 clocks cycles faster than before.

 

[WMXZ]

or something like this?
in cmsis_gcc.h

  \brief   Enable IRQ Interrupts
  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __enable_irq(void)
{
  __ASM volatile ("cpsie i" : : : "memory");
}


/**
  \brief   Disable IRQ Interrupts
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
}

this is what my VSCode found if I looked up the definition (F12: go to definition)
I'm using the CMSIS library for FFT so that is included from there

edit
from imxrt.h

#define __disable_irq() __asm__ volatile("CPSID i":::"memory");
#define __enable_irq()  __asm__ volatile("CPSIE i":::"memory");

 

[WMXZ]

a side question
in arm_dcache* functions we find

	asm volatile("": : :"memory");
	asm("dsb");

if I take disable_irq() we have

#define __disable_irq() __asm__ volatile("CPSID i":::"memory");

how should we read this?
IOW, could we use

__asm__ volatile("dsb":::"memory");

or is the order: first "": : :"memory" and then "dsb" , of importance?

 

[Frank B]

I was asking about memory prefetches.
There are hint instructions that tell the CPU that an access to a specific memory location is likely in the near future.
PLD for Data, PLI for instructions. The CPU then can instruct the memory interface to do steps that lead to a faster access.
For the cache, it could be a prefetch?

As I learned now, only the instruction cache does automatic prefetch. Is that correct?
SO, i could imagine a speedup for data, for example before loops (i.e. like a memcpy, fast caluclation that read an array etc)
I have no idea how much impact they have, and that's why I ask.
Are they useful? If I look at the audio library, it would be full of use cases.

a side question
in arm_dcache* functions we find

    asm volatile("": : :"memory");
    asm("dsb");

if I take disable_irq() we have

#define __disable_irq() __asm__ volatile("CPSID i":::"memory");

how should we read this?
IOW, could we use

__asm__ volatile("dsb":::"memory");

or is the order: first "": : :"memory" and then "dsb" , of importance?

:::memory is a hint for the compiler. It tells him to do all load/store instructions before the barrierer, If I'm right.
For the interrupts I can only imagine a few corner cases where this makes sense: When data need to be written _before_ an interrupts occurs. If you write to the vector table, for example.
Are there more cases?

 

[Frank B]

I now found this for you:
https://stackoverflow.com/questions/16032202/how-to-use-pld-instruction-in-arm


Edit: GCC adds it when told to do so: https://godbolt.org/z/Mxq5Y5 (this example is, of course, pointless)

However, my question remains.

 

[Frank B]

ARM shows an example:

extern int data1;
extern int data2;
volatile int *interrupt = (volatile int *)0x8000;
volatile int *uart = (volatile int *)0x9000;
void get(void)
{
    __pld(data1, data2);
    while (!*interrupt);
    *uart = data1;        // trigger uart as soon as interrupt occurs
    *(uart+1) = data2;
}

Note, it uses the ARM compiler. The syntax is a little different. You can substitute the __pld intrinsic by 2x __builtin_prefetch