// some defines:
#define GPT1 1
#define GPT2 2
#define GPT_BOTH 3
#define GPT_BOTH_GPT2FIRST 4
#define GPT_CLOCK_SOURCE 3 // 3 = external GPT clock, note you can set internal sources see section 52 of chip datasheet
#define GATE_CLOCK_FREQ 10000000
#define NO_INTERRUPT 0 // Counter ISR setup control variable
#define ROLLOVER 1 // ISR setup
#define COMPARE_RESET 2 // ISR setup
#define COMPARE_FREEZE 3 // ISR setup
// Example lines that call the init function:
initGPTCounter(GPT1,GPT_CLOCK_SOURCE,0,ROLLOVER); // Sets up GPT1 with clock input on pin 14, clock source options 1..3.
initGPTCounter(GPT2,GPT_CLOCK_SOURCE,gateCountVal,COMPARE_RESET); // Sets up GPT2 with clock input on pin 25, params: GPTn, clkSource, compare1 value,interrupt type)
initGPTCounter(GPT2,GPT_CLOCK_SOURCE,0,NO_INTERRUPT); // Sets up GPT1 with clock input on pin 14, clock source options 1..3.
initGPTCounter(GPT1,GPT_CLOCK_SOURCE,gateCountVal,COMPARE_FREEZE); // Sets up GPT2 with clock input on pin 25, params: GPTn, clkSource, compare1 value,interrupt type)
// start function also:
startGPTCounter(GPT_BOTH); // GPT_BOTH starts GPT1 first, gives most accurate count see comments in function
void initGPTCounter(uint8_t GPTn, uint8_t clkSource, uint32_t compare1, uint8_t interrupt)
{
if (GPTn==GPT1)
{
CCM_CCGR1 |= CCM_CCGR1_GPT(CCM_CCGR_ON) ; // enable GPT1 module
GPT1_CR = 0;
GPT1_SR = 0x3F; // clear all prior status
GPT1_CR = GPT_CR_CLKSRC(clkSource); // GPT_CR_FRR is clear so that compare 1 events will reset counter,clkSource = 3 = external clock
GPT1_CR |= GPT_CR_ENMOD; // ENMOD set in GPTn_CR reg means that counter is always reset to zero whenever enabled/reenabled
*(portConfigRegister(25)) = 1; // ALT 1 Clock pin is 25
if (interrupt == ROLLOVER && compare1 == 0) setupIntGPTRollover(GPT1); // Enables timer rollover interrupt on GPTn (GPT1 #define = 1)
else if (interrupt == COMPARE_RESET && compare1) setupIntGPTCompare(GPT1,compare1,interrupt); // Setup compare interrupt with counter reset on compare 1 match GP1
else if (interrupt == COMPARE_FREEZE && compare1) setupIntGPTCompare(GPT1,compare1,interrupt); // Interrupt routines can freeze counters when called (interrupt==3), interrupt < 3 = continue counting
}
else if (GPTn==GPT2)
{
CCM_CCGR0 |= CCM_CCGR0_GPT2_BUS(CCM_CCGR_ON);
GPT2_CR = 0;
GPT2_SR = 0x3F; // clear all prior status
GPT2_CR = GPT_CR_CLKSRC(clkSource); // GPT_CR_FRR is clear, clkSource 3 = external clock
GPT2_CR |= GPT_CR_ENMOD; // ENMOD set = reset counter to zero on every enable/reenable
IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 8; // select input pin (14)
IOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT = 1;
if (interrupt == ROLLOVER && compare1 == 0) setupIntGPTRollover(GPT2); // Enables timer rollover interrupt on GPTn (GPT1 #define = 1)
else if (interrupt == COMPARE_RESET && compare1) setupIntGPTCompare(GPT2,compare1,interrupt); // Setup compare interrupt/counter reset on compare 1 match GP2
else if (interrupt == COMPARE_FREEZE && compare1) setupIntGPTCompare(GPT2,compare1,interrupt); // Set up ISR that freezes counters when called
}
void startGPTCounter(uint8_t GPTn)
{
if (GPTn == GPT_BOTH) {GPT1_CR |= GPT_CR_EN; GPT2_CR |= GPT_CR_EN; return;} // Enable both GPT 1 and 2 near-simultaneously, GPT1 first
if (GPTn == GPT_BOTH_GPT2FIRST) {GPT2_CR |= GPT_CR_EN; GPT1_CR |= GPT_CR_EN; return;} // GPT 2 enabled first
if (GPTn == GPT1) {GPT1_CR |= GPT_CR_EN; return; } // Enable only GPT1. Counter will reset to start from zero assuming GPT_CR_ENMOD is set by init()
if (GPTn == GPT2) {GPT2_CR |= GPT_CR_EN; return;} // Enable only GPT2
}