Forum Rule: Always post complete source code & details to reproduce any issue!
Results 1 to 14 of 14

Thread: Teensy 4.1 Suitability

  1. #1
    Junior Member
    Join Date
    Apr 2021
    Posts
    6

    Teensy 4.1 Suitability

    My plans are to drive 3 displays (using Quad SPI to Bridgetek BT815/6 boards) and be able to store values to memory persistently multiple times per second (at least) for possibly years, but at the same time able to handle unpredictable power loss.

    Can I install other SPI/QSPI devices in the the PSRAM/Flash ram locations, assuming I write my own software to interact with them, or are they specifically hard coded to only work with PSRAM and the Flash modules?

    Specifically FRAM or some other NVRAM.

    Thanks in advance for any help.

  2. #2
    Senior Member+ defragster's Avatar
    Join Date
    Feb 2015
    Posts
    13,916
    IIRC > @mjs513 wrote support for MRAM - though smaller - they work. That came about as part of the LittleFS IIRC and the support for that is in current TD 1.54 Beta.

    That LittleFS thread and the PaulStoffregen github repository shows the recognized chips.

    NOR and MRAM : } known_chips[] = {

    NAND FLASH : } known_chips[] = {

  3. #3
    Junior Member
    Join Date
    Apr 2021
    Posts
    6
    So the pins for those slots are accessible and I can put any SPI like SOIC-8/SOP-8 chip there as long as I manage them manually?


    I was specifically planning to use a CY15E064Q-SXET in the second slot. It's a 64K memory chip, but considering I only need around 1K, it should do fine.

    As for the first I would probably just use the recommended PSRAM, which is extreme overkill for my use case. Actually most of this is likely massively overkill for my use case.
    Last edited by csdgn; 04-17-2021 at 03:45 AM.

  4. #4
    Senior Member+ defragster's Avatar
    Join Date
    Feb 2015
    Posts
    13,916
    Any chip on those pins to memory map with processor supported addressing on QSPI needs setup and interface as done in the linked sources for supported chips.

    The linked chip doesn't seem to support QSPI - so interface would rely on slower SPI interface. It seems the used chips power up as SPI devices and are then put into QSPI mode.

    If only 1K is needed the supported MRAM's should work? The smallest 1Mb of those gives 128 KB

    If interfacing a new chip is desired and QSPI functional then please contribute ... or explain how cool it is and @mjs513 might look into it.

  5. #5
    Senior Member PaulStoffregen's Avatar
    Join Date
    Nov 2012
    Posts
    24,088
    The main issue I can see is whether FlexSPI can be configured to generate such a slow SPI clock speed. I seem to recall there's a bit somewhere which cuts all the clock speeds in half. But I'm not sure if even that and the slowest clock settings can get FlexSPI down to just 16 MHz.

    Programming FlexSPI requires figuring out how to set up its LUTs, which is a very different programming experience than normal SPI hardware. But now with PSRAM and many chips supported by LittleFS, there's plenty of example code, so this isn't as hard as it used to be.

    Even if FlexSPI doesn't work out, you could always just bitbang, since all those pins can also be configured for normal GPIO rather than FlexSPI. Just remember to use delayNanoseconds() before toggling SCK, so your code running at 600 MHz doesn't exceed the 16 MHz max speed that FRAM can handle.

    You'll also need to find a 3V version of that chip. The CY15E064Q datasheet says it's a 5V part. The power supplied to those pads on the bottom of Teensy 4.1 is 3.3V, and the pins are designed to work only with 3.3V signals.

  6. #6
    Senior Member+ defragster's Avatar
    Join Date
    Feb 2015
    Posts
    13,916
    Good on the missed details Paul - stopped scanning after seeing it doesn't support QSPI ... but has to be 3.3V part. And even some of the supported parts IIRC have slower SPI interface than when jumping to QSPI mode. Going SPI at slower clock could make them significantly slower - though for small access region of 1KB the cache might hide that.

  7. #7
    Junior Member
    Join Date
    Apr 2021
    Posts
    6
    Good points all around, the ones in the linked LittleFS are Nor, NAND or FRAM chips. I did not see any MRAM, but perhaps I misread.

    That being said I am looking at the AS3004204-0108X0PSAY, as it meets the voltage, performance, speed and interface requirements, and it is also currently available for purchase. It is larger than I need but that's not a bad thing. It is a PSRAM, but its Persistent, rather than Psuedo.

    Thanks for your advice in this matter. I would have made serious mistakes otherwise.

  8. #8
    Senior Member+ defragster's Avatar
    Join Date
    Feb 2015
    Posts
    13,916
    FRAM is one makers Ferro RAM ( i.e. mag with retention) where the other is called MRAM

    Look up the parts on digikey { in the 'known_chips[]' or probably links in the thread }- they are similar function just diff names and they offer retention through Ferro/Magnet storage.

    Programming supplied and tested to work. Those in smaller capacity are not too expensive ... but they run up $$$ quickly going larger then indicated as needed.

  9. #9
    Junior Member
    Join Date
    Apr 2021
    Posts
    6
    Yep, spent about 20 USD per chip on the one I picked out.

  10. #10
    Senior Member+ defragster's Avatar
    Join Date
    Feb 2015
    Posts
    13,916
    This is the one "F-RAM™" ( F-RAM is a Cypress TM ) :: $13.20 1Mbit >> cypress-semiconductor-corp/FM25V10-G

    Another part that works is this $4.41 MRAM 1Mbit >> rohm-semiconductor/MR45V100AMAZAATL :

    Both of those are 128 KB and detailed as : Non-Volatile FRAM (Ferroelectric RAM)

    Links are from my Digikey order history - yikes - $20 would buy one of each with some spare $ to cover shipping.

    BUT : those two are both SPI only - so tested on SPI pins with mjs513 code - not direct soldered to T_4.1 QSPI pads - been months since testing so just recalling that ...

    Using the FLASH chips cost less for even more extra space - and do direct solder for QSPI usage and provide reliable non-volatile usage at good speed.

  11. #11
    Junior Member
    Join Date
    Apr 2021
    Posts
    6
    So is there an exposed pin for QSPI outside of the memory chip interfaces? Specifically the d0,d1,d2,d3,sck for it.

  12. #12
    Senior Member+ defragster's Avatar
    Join Date
    Feb 2015
    Posts
    13,916
    Quote Originally Posted by csdgn View Post
    So is there an exposed pin for QSPI outside of the memory chip interfaces? Specifically the d0,d1,d2,d3,sck for it.
    The only presentation of the QSPI lines {pins#48-54} on T_4.1 are on the bottom side pads. Except for unique CS on each set - the pins are the same on both. Newest T_4.1 card or the info on PJRC.com has image with notes.

  13. #13
    Junior Member
    Join Date
    Apr 2021
    Posts
    6
    Yes, but I was hopeful there was a way to get it aside form those. I guess I could bitbang it, but it has a 30Mhz bus and I need to drive 3 devices. I don't know if that would be any faster than just using SPI or Dual SPI (if that's even supported by the normal SPI interface).
    Last edited by csdgn; 04-21-2021 at 11:17 PM.

  14. #14
    Senior Member PaulStoffregen's Avatar
    Join Date
    Nov 2012
    Posts
    24,088
    You might end up exceeding the 30 MHz spec if your bitbanging code is efficient.

    We saw problems with functions like shiftOut() and libraries like ShiftPWM during the beta testing and in the early days of Teensy 4.0. Bitbanging code that was assumed would always be so slow that no delays are needed can become too fast when the CPU runs at 600 MHz.

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •