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Thread: Audio Board and alternative pin mappings - 2 Assumptions and a Question

  1. #1
    Senior Member Davidelvig's Avatar
    Join Date
    Aug 2015

    Audio Board and alternative pin mappings - 2 Assumptions and a Question

    I have a few Teensy audio adaptors, and want to add their functionality to a custom Teensy 3.2-based board I've built.
    I need all of the touch pins on the Teensy for other puposes.
    So want to use alternate I2C pins (best would be pins 29 & 30) on the standard Teensy 3.2 back-side.
    I think I can just declare these pins using:
    - Wire.setSDA(pin)
    - Wire.setSCL(pin)
    and if I've wired the Audio Board pins correctly, it should work.

    Am I correct?

    Also, I'd like flexibility in the I2S pin mappings
    I see the standard Teensy 3.2 pins would be
    • MCLK 11 Audio Master Clock, 11.29 MHz
    • BCLK 9 Audio Bit Clock, 1.41 or 2.82 MHz
    • LRCLK 23 Audio Left/Right Clock, 44.1 kHz
    • DIN 22 Audio Data from Teensy to Audio Shield
    • DOUT 13 Audio Data from Audio Shield to Teensy

    I don't see anywhere to configure these pins in the Teensy libraries.
    I'm assuming these are fixed (though I see in the MK20DX256VLH7 documentation reference to a TXD0/TXD1 and RXD0/RXD1)

    Should I assume these pins are fixed, and as such, work around them by using alternate SPI MOSI and CLK?

    Lastly, I now have good experience with VS1053 Synth chip fro VLSI. I've been using it for a MIDI synth and for headphone output.

    With the Audio Shield, I would only use the VS1053 for a MIDI Synth, and route its sound back through the audio library.
    The VS1053 has stereo line out and I2S out.

    Can I hook this up as an input to the Teensy audio library using its I2S output.
    (I'm not yet I2S savvy... is there a Master/Slave thing I need to understand?


  2. #2
    Senior Member
    Join Date
    Jul 2020
    SCL2/SDA2 are not alternates for SCL1/SDA1, they are a different hardware module, I think its Wire1 as opposed to Wire,
    but double check please. Alternates are multiplexed to the same hardware module.

    I2S pin usage is described for the relevant objects in the audio library design tool - just select an i2s input or output object
    for the docs to appear.

  3. #3
    Senior Member Davidelvig's Avatar
    Join Date
    Aug 2015
    Thanks, MarkT.

    1) I see that control_sgtl5000.cpp uses Wire.h and Wire.begin
    and the included WireKinetis.h defines Wire1, Wire2... etc.

    Should I assume that I have to modify control_sgtl5000.cpp and change all "Wire." instances to "Wire1."

    2) Regarding I2S output from the VS1053, I think it might work (and I could just connect as an input to the Teensy Audio Library).
    I think I recall that the Teensy must provide the clock for the I2S bus, so the VS1053's clock option must be disabled.
    It seems to have a register with an enable bit for that:
    I2S_CF_MCLK_ENA enables the MCLK output. The frequency is either directly the input clock (nominal 12.288 MHz), or half the input clock when mode register bit SM_CLK_RANGE is set to 1 (24-26 MHz input clock).
    Thanks again.

    Any advice about the wisdom of modifying control_sgtl5000.cpp?

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