TLC5916 SPI cascade

[ghostintranslation]

Hi,

I'm usually using I2C devices, but this time I'm interested in the TLC5916 which is SPI:
https://www.ti.com/lit/ds/symlink/t...-digikeymode-dsf-pf-null-wwe&ts=1622292689320

Usually from what I understand is that each SPI device has a select pin so that it set the device to listen to the bus. But in this documentation they also show a "cascade" implementation:


I see the SDO of the first device going in the SDI of the next device, but how does that work then? In this configuration can I still address each device separately or are they all going to be acting as just the same one device?

Thanks

 

[ghostintranslation]

Actually I think I got it, when LE is high it's listening for data on SDI, and as long as it keeps receiving data it's pushing the previous data on SDO and when OE is low it's setting the outputs according to the data it received.

Does that sound correct?

 

[MarkT]

Actually I think I got it, when LE is high it's listening for data on SDI, and as long as it keeps receiving data it's pushing the previous data on SDO and when OE is low it's setting the outputs according to the data it received.

Does that sound correct?

Normally you'd keep OE asserted, the LE is what clocks the data onto the latches. in normal mode
shifting happens on every rising clock edge, and the shift register state is only copied to the output latches
with LE being asserted, so a single pulse on LE after shifting in all the data will update all chips outputs
simultaneously.