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Thread: Obscure question about AIPS-Lite and FTM2_MOD register addresses in Teensy 3.6

  1. #1
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    Obscure question about AIPS-Lite and FTM2_MOD register addresses in Teensy 3.6

    I'm trying to understand the Teensy 3.6 at the register level. One thing that puzzles me is that the address for FTM2_MOD is defined in kinetis.h as 0x400B8008, but in the manual the address is 4003_A008 (page 1141). My question is why aren't these addresses the same?

    The manual explains (page 106) that the peripheral bridge is set up with AIPS-Lite0 at 0x4000_00000x4007_FFFF and AIPS-Lite1 at 0x4008_00000x400F_EFFF.
    Based on this, I hypothesized that the two addresses are equivalent, going through different peripheral bridges. But two things confuse me. First, accessing the address in the manual crashes the Teensy. Second, the FTM2_MOD address from the manual ends in A008, while the code's address ends in 8008 so it's not a straightforward mapping from AIPS-Lite0 to Lite1.

    Code:
    void setup() {
        Serial.println(*(uint32_t *)0x400b8008, DEC);
        Serial.println("Printed FTM2_MOD");
        Serial.println(*(uint32_t *)0x40038008, DEC); // works
        Serial.println("Printed FTM0_MOD");
        Serial.println(*(uint32_t *)0x4003A008, DEC); // crashes?
        Serial.println("Printed alternate FTM2_MOD"); // not printed
    }
    So why does the Teensy code use a different FTM2_MOD address from the one in the manual, which apparently doesn't work?

  2. #2
    Senior Member+ defragster's Avatar
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    Doc/Header errors can happen - as devices and elements get used ... starting in Beta ... errors get corrected.

    If you can confirm and get functionality the change will be made. Doing a Pull Request against the github file makes it easy with links to to relevant posts/docs.

    Does the device have a clock to start? Any device used without being enabled will result in a fault/crash.

  3. #3
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by shirriff View Post
    One thing that puzzles me is that the address for FTM2_MOD is defined in kinetis.h as 0x400B8008, but in the manual the address is 4003_A008 (page 1141). My question is why aren't these addresses the same?
    You can find the alternate FTM2 address documented in the table on page 113.

    We use the alternate address because it matches the (only) FTM2 address for MK20 chip on Teensy 3.2.



    The manual explains (page 106) that the peripheral bridge is set up with AIPS-Lite0 at 0x4000_0000–0x4007_FFFF and AIPS-Lite1 at 0x4008_0000–0x400F_EFFF.
    Based on this, I hypothesized that the two addresses are equivalent, going through different peripheral bridges.
    Yes, that's right. It's as the footnote on page 114 says.



    But two things confuse me. First, accessing the address in the manual crashes the Teensy.
    It's as Defragster mentioned "Any device used without being enabled will result in a fault/crash". It's a problem that's come up over and over again on this forum when people try to craft custom code to talk to peripherals on Teensy 3.x. If you don't first enable the peripheral, you get a memory fault when trying to access its registers.

    The confusing part is there are 2 different FTM2 enable bits. One is in the SIM_SCGC3 register (bit 24) documented on page 257. The other is in the SIM_SCGC6 register (bit 26) documented on page 263.

    This text on page 263 explains the situation:

    DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
    accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
    When accessing through AIPS0, define the clock gate control bits in SCGC6. See the
    Chip Configuration chapter for the base addresses of RNGA, FTM2, and DAC0 accessed
    via AIPS0 and AIPS1.
    Because we use the alternate address in AIPS1, the startup code is setting the FTM2 bit in SCGC3, but not setting the FTM2 bit in SIM_SCGC6.

    If you want to access FTM2 using the 0x4003A008 address, you need to enable it via SIM_SCGC6. I have no idea what happens if you enable it in both SIM_SCGC3 and SIM_SCGC6. To be honest, I've never even tried to access this timer via AIPS0. When I designed Teensy 3.5 & 3.6, the path of least resistance was to just go with AIPS1 which matches what we had done for years on Teensy 3.1 & 3.2. If it ain't broke...



    Second, the FTM2_MOD address from the manual ends in A008, while the code's address ends in 8008 so it's not a straightforward mapping from AIPS-Lite0 to Lite1.
    No, it's not the same low 19 bits (or slot number) on AIPS0 versus AIPS1. And in general, you rarely see that sort of design on these modern chips. The days where one tight-knit team designs the whole chip with a highly consistent and optimized approach are long gone.

  4. #4
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    Thank you Paul for your detailed answer!

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