@Jetsream:
In further consideration of your interesting problem, I think I have figured out why your getting all x0FFFF's back from the A/D.
If you look carefully at the MCP33121 data sheet page 38 timing diagram, you will find out why you are getting all x0FFFF's. The length of the CNVST positive cycle (rising edge to falling edge) is critical. If the CS/ signal from the Teensy is very short CS/ high state the A/D will not have time to complete the conversion when the Teensy SPI starts to shift out the data bits. As note 2 from the timing diagram says: "Any SCLK toggling events (dummy clocks) before CNVST is changed to "Low" are ignored". If you look at Timing Diagram for SDO you will see that SDO is in Hi-Z (tristate) for all the tCNV time plus tEN time, which is the convert time plus the time for enabling the SDO pin. (The convert time is set by an internal clock and cannot be changed)
As you can see you are trying to sample the DIO pin before the conversion is complete where the SDO pin is in Hi-Z which will give you a reading of x0FFFF's. Now after reviewing the LPSPI section of the RT1060 processor pages 2823-2824 you can see that the timing of the SCKPCS, PCSSCK, DBT, and SCKDIV can be set in the LPSPI Clock Configuration Register (CCR). I think if you experimented with these settings you could probably make this A/D work with the Teensy.
However if you have no idea what I am talking about with the last sentence perhaps you should consider using a more friendly A/D like the LTC2367-16, which has BUSY pin which you could use as an interrupt, thus eliminating some of these odd timing problems.
Regards,
Ed