SPI issues with external ADC

[UhClem]

The time required to hold CNVH high is 10ns. It would require an exceptionally fast micro to violate that. I would worry with a Teensy 4.1 but not with a 3.2. The conversion time of 700ns is a different story.

An easy way to manage this is to lower CNV, read the data, and raise CNV. Do not repeat for a microsecond or so at least. Note that the ADC is sampling data while CNV is low for its next conversion.

 

[Jetsream]

@Jetsream:
In further consideration of your interesting problem, I think I have figured out why your getting all x0FFFF's back from the A/D.
If you look carefully at the MCP33121 data sheet page 38 timing diagram, you will find out why you are getting all x0FFFF's. The length of the CNVST positive cycle (rising edge to falling edge) is critical. If the CS/ signal from the Teensy is very short CS/ high state the A/D will not have time to complete the conversion when the Teensy SPI starts to shift out the data bits. As note 2 from the timing diagram says: "Any SCLK toggling events (dummy clocks) before CNVST is changed to "Low" are ignored". If you look at Timing Diagram for SDO you will see that SDO is in Hi-Z (tristate) for all the tCNV time plus tEN time, which is the convert time plus the time for enabling the SDO pin. (The convert time is set by an internal clock and cannot be changed)
As you can see you are trying to sample the DIO pin before the conversion is complete where the SDO pin is in Hi-Z which will give you a reading of x0FFFF's. Now after reviewing the LPSPI section of the RT1060 processor pages 2823-2824 you can see that the timing of the SCKPCS, PCSSCK, DBT, and SCKDIV can be set in the LPSPI Clock Configuration Register (CCR). I think if you experimented with these settings you could probably make this A/D work with the Teensy.
However if you have no idea what I am talking about with the last sentence perhaps you should consider using a more friendly A/D like the LTC2367-16, which has BUSY pin which you could use as an interrupt, thus eliminating some of these odd timing problems.
Regards,
Ed

I am sorry for the late reply guys. I had to travel for work and was busy trying to learn about the ins&outs of SPI and the LPSPI Clock Config Registers. Unfortunately, I just can´t figure out how to get the MCP33121 to work.

@sbfreddie: thanks for suggesting the LTC2367-16. It reads great, but unfortunately, it is impossible to get. Any alternatives? The LTC has a lead time of more than 30 weeks atm..

 

[Jetsream]

Or another idea.. the sensors signal saturates at 4.3V and has a minimum of 0.8V. Is there a way, a circuit (maybe using an opamp?) to substract 0.8V from the incoming signal?
lets say.. I have 4V incoming from the sensor, I substract 0.8V get 3.2 and therefor make it readable for the Teensy and it´s internal adc.
Of course, this would need to work at 200ksps..

 

[sbfreddie]

Jetsream:
You could use either a resistor divider, or an Op-amp with negative gain. So keep in mind that most of these A/D's do not have buffered inputs so they like to be driven from a low output impedance source.
Here is a quote from an application note DN308f from Linear Technology Corp.:
"A/D converters have sample apertures that are extremely narrow (infinitesimal as far as mathematicians are concerned) and make demands on upstream circuitry far in excess of what the innocent looking sample rate would imply. In addition, when an A/D converter takes a sample, it applies a small capacitor to its inputs causing a fair amount of glitch energy and expects the voltage on the capacitor to settle to the true value very quickly. Finally, the LTC1864 has a 20MHz analog input bandwidth and can be used in undersampling applications, again requiring a source bandwidth and settling speed higher than the Nyquist criterion would imply."
Perhaps reading some of Analog Devices other app notes might be in order, might I suggest AN282, and AN501 for starters. There is a lot of info available to you, google is your friend.

Regards,
Ed