Hi All,
I am operating a Teensy 4.0, 600MHz clock, and a PWM frequency in the vicinity of 800kHz to 1MHz on pin 9. I have several questions about the state of a PWM output pin when operating at a PWM frequency established by an analogWriteFrequency command. What I want to accomplish is to establish the PWM frequency at a very low duty cycle (no problem doing that) , and after the PWM pulse terminates I would like to override the state of the digital I/O on the PWM pin by writing the pin HIGH followed by a delayNanoseconds() and then writing the pin LOW after the delay has elapsed. The pulse I want to generate by this override is considerably shorter than the period of the PWM frequency.
The problem I am trying to solve is to achieve finer resolution of duty factor on that pin than can be achieved by the analogWrite of duty factor. I have about 7 bits of resolution in duty factor but that is insufficient for the application I have. It is apparently limited by the 150MHz clock used to control the pulse width in the PWM routine.
The device I am driving will not respond to a pulse shorter than 10nsec, so I can allow a low duty factor pulse to expire at the PWM frequency and follow that by a more precisely adjustable pulse width.
So the question is how is the PWM pin being held LOW after the termination of the HIGH state attributable to the duty factor in the PWM code? Is it an active pulldown? Can the PWM pin be directly written HIGH inspite of the normal LOW state following the PWM pulse? Are there adjustments of the digital I/O pin characteristics that would permit this to be done?
Thanks for any suggestions
I am operating a Teensy 4.0, 600MHz clock, and a PWM frequency in the vicinity of 800kHz to 1MHz on pin 9. I have several questions about the state of a PWM output pin when operating at a PWM frequency established by an analogWriteFrequency command. What I want to accomplish is to establish the PWM frequency at a very low duty cycle (no problem doing that) , and after the PWM pulse terminates I would like to override the state of the digital I/O on the PWM pin by writing the pin HIGH followed by a delayNanoseconds() and then writing the pin LOW after the delay has elapsed. The pulse I want to generate by this override is considerably shorter than the period of the PWM frequency.
The problem I am trying to solve is to achieve finer resolution of duty factor on that pin than can be achieved by the analogWrite of duty factor. I have about 7 bits of resolution in duty factor but that is insufficient for the application I have. It is apparently limited by the 150MHz clock used to control the pulse width in the PWM routine.
The device I am driving will not respond to a pulse shorter than 10nsec, so I can allow a low duty factor pulse to expire at the PWM frequency and follow that by a more precisely adjustable pulse width.
So the question is how is the PWM pin being held LOW after the termination of the HIGH state attributable to the duty factor in the PWM code? Is it an active pulldown? Can the PWM pin be directly written HIGH inspite of the normal LOW state following the PWM pulse? Are there adjustments of the digital I/O pin characteristics that would permit this to be done?
Thanks for any suggestions