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Thread: SPI variant question

  1. #1
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    SPI variant question

    I've been looking at fast dual ADC chips, with a possible SDR application for the I/Q channels. Most audio codecs run out of gas above 192KSPS (if you want to stick with the data sheet anyway) but there are a number of dual 16-bit ADC's that are specified up to 2MSPS (and beyond), like the MAX1198. However. It appears that dual ADC's like this don't use the I2S interface, but some variant of SPI. For instance, the MAX1198 uses a SPI interface that has one clock and TWO data channels. My question: does Teensyduino support that?? There's nothing to suggest it can, based on what I've seen in the online SPI library docs.

    Thanks
    Mark

  2. #2
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    Which Teensy?

    Note: I don't know any library that supports it directly...
    But for example T4.x, the LPSPI chapter talks about Dual/Quad transfers.

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    Specifically, the 4 series. When you say "LPSPI chapter" are you referring to the data sheet?

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    Table 50-9 in the processor reference manual shows an example of a FlexIO setup configured as an SPI master. That would be a good starting point. It should be possible to allocate a third shifter for the second data stream from the A/D.

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    Senior Member+ KurtE's Avatar
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    Yes reference Manual: https://www.pjrc.com/teensy/IMXRT1060RM_rev2.pdf


    Chapter 48 for Low Power SPI

    You will see the pins in section 48.2.5 talk about SIN/SOUT as Data[0] and Data[1] and talk about dual and quad data...

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    Some online searching has indicated that the dual data mode for SPI transfers data on both the rising and falling edge of SCK. For instance, see https://embeddedinventor.com/quad-sp...-need-to-know/. So the data still is coming into just one pin. The dual ADC I'm interested in has TWO data outputs that represent two (possibly very different) values.

    The quad mode probably does support two input streams, but they are assumed to be one interleaved data word, not two separate data streams. That also is a nonstarter for two separate data streams.

    I get the impression that the dual and quad modes were devised primarily for flash memory, not to support "weird" SPI devices. But the FlexIO subsystem should be able to do it.

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    The T4 has two 1MSPS ADCs inbuilt. Might be worth a try to just use them? As far I know you can overclock them, too (might mean a bit more noise)

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    Quote Originally Posted by Mcu32 View Post
    The T4 has two 1MSPS ADCs inbuilt. Might be worth a try to just use them? As far I know you can overclock them, too (might mean a bit more noise)
    The performance of a QSD-based SDR is highly dependent on the ADC. While the built-in ADC's sample rate is fast enough to permit decoding wideband FM, losing 4 bits (12 vs. 16) isn't something I want to do. The other advantage of an external ADC is the ability to use it in true differential mode -- also something useful with regard to this type of SDR.

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    For FM demodulation you are not interested in the amplitude.
    It is even a known principle to overdrive the signal and make it rectangular to remove it's influence. You need the frequency /time, not the amplitude. You don't want the influence of the amplitude. It's not even modulated...
    Last edited by Mcu32; 09-23-2021 at 06:09 AM.

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    Hi,
    The solution would involve using two SPI channels - one working in slave mode on the Teensy. You would connect one output data line from your ADC to the MISO pin for the Teensy master SPI input, and connect the second to the MOSI pin for the Teensy slave SPI channel. You would also have to connect the CS and SCK outputs from the master to the CS and SCK inputs of the slave channel. The problem then is implementing SPI slave mode on the Teensy,
    All the best,
    Alan

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    Quote Originally Posted by AlanK View Post
    Hi,
    The solution would involve using two SPI channels - one working in slave mode on the Teensy. You would connect one output data line from your ADC to the MISO pin for the Teensy master SPI input, and connect the second to the MOSI pin for the Teensy slave SPI channel. You would also have to connect the CS and SCK outputs from the master to the CS and SCK inputs of the slave channel. The problem then is implementing SPI slave mode on the Teensy,
    All the best,
    Alan
    That's an interesting idea. Examination of the reference manual indicates that there are 4 LPSPI blocks, and they can be individually configured as a Master or Slave. I'll have to look at the IOMUX assignments to see what's available on a Teensy4.0 or 4.1. Since just one SPI channel is called out on the Teensy4.0 schematic, it probably will be necessary to do some register manipulation to use a second SPI channel.....IOMUX one(s) plus the relevant DMA and LPSPI registers.

    Thanks for the suggestion!
    Mark

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    SCK2, CS2, MOSI2 and MISO2 are available on the back of the T4.0. They are pins 37, 36, 35 and 34 respectively. Not real easy to use, being part of the SD card socket footprint. However, I have a stereomicroscope that I use when assembling PCB's that have SMT components on them. I still wouldn't want to hand-solder 0201's, but larger components aren't too bad.

    While SCK1 and MOSI1 also are available on the back, CS1 and MISO1 are nowhere to be found. Too bad, because their pads are larger and would be much more robust when soldering to them. Oh well....

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