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Thread: Emulating Commodore Ram with a Teensy4(.1)

  1. #1
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    Emulating Commodore Ram with a Teensy4(.1)

    Ok so i got a couple of old 65xx series processors. The old fellas that you'd find in old computers like the Commodore.
    I want to play around with them a bit. learn how they work through practice. Thing is is that i don't have the ram nor a simple way to load such ram with instructions.

    Now. i have this idea of Emulating the 64KB RAM with a Teensy4(.1). Which in a perfect world would let me pre-load machine-code and experiment that way.
    The thing is that i don't know if the Teensy is fast enough to do this. I want to run the processors at 1-2Mhz and i know that they can perform a memory operation every cycle.
    So the Teensy would have to be very fast at reading the 16-bit address and either loading from or writing to memory data through the 8-bit data bus.


    Which leads me to my question: Think it is feasible to emulate Ram this fast (<500ns) with a Teensy?
    I know ARMs tend to be slower on the GPIO than with memory to memory operations so i figured i'd double check.
    I would think 800Mhz would be enough to get decent speed with some tricks like direct manipulation of the GPIO registers.



    (P.S. I know i could just emulate a 6502 outright, but working with the real deal seems more fun)

  2. #2
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    Sounds like fun. Would something similar to <this> be close to what you are looking for ?? It at least answers the speed question (specs 200ns, where you say you need <500ns). Sounds like you'd need the ability to "write" as well as "read", but this may provide you a starting point to build upon . . .

    Mark J Culross
    KD5RXT

  3. #3
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    Quote Originally Posted by kd5rxt-mark View Post
    Sounds like fun. Would something similar to <this> be close to what you are looking for ?? It at least answers the speed question (specs 200ns, where you say you need <500ns). Sounds like you'd need the ability to "write" as well as "read", but this may provide you a starting point to build upon . . .

    Mark J Culross
    KD5RXT

    That is indeed very close. same premise, albeit with Tristate Data-bus controlled by a Read/write and CS/address-decoding.
    I think i should be able to get what i want via a similiar code. Maybe cut off some time by using the exposed 16-bit IO bus of the 4.1 for reading in a single hit (rather than individually copy and shift each IO bit like the eprom emulator) and use Interrupts for handling the write portions. Wiring is looking to be a mess though since the teensy has no ordering in the pins.


    This tells me what i needed to know. That it should be feasible. though address decoding for peripherals might have to be done via discrete logic. Also i forgot about the 65xx's own address setup time so timing is looking a wee bit tighter(~300ns).
    Either way. Plenty of experimentation awaits. Thanks for linking me to the Eprom emulator project.


    Good. Alternative solutions where to use an FPGA (costly), figure out how to bootload a ram chip through the 65xx (could be fun, but a bit down the line) or use discrete logic to give an external controller access to the RAM.
    Last edited by Foxhood; 09-20-2021 at 09:25 AM. Reason: correction

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