Some recent discussion about driving parallel interfaces with FlexIO has got me thinking about developing some kind of general library. Is this something that would be useful to the community?
Ideas for features:
If your data pins are contiguous and in order (with respect to FlexIO pin ordering, not Teensy pin numbers), a more efficient process could be used that skips the buffering step and uses the source data without reordering bits, which could be done with nearly zero CPU usage or lag. But this wouldn't be a big deal unless you need maximum speed.
There would be some restriction on the available pins. They all have to be from a single FlexIO peripheral, and the clock pin (if desired) has to have a lower or higher FlexIO pin number than all the data pins. Some documentation to show possible pin configurations would be needed. The maximum number of pins would be as follows:
Ideas for features:
- Parallel output with a flexible number and order of pins
- 4, 8, 16 bit interfaces possible (up to 22)
- Max sustained speed in the 20-50 MHz range
- Hardware clock pin output (optional)
- Non-blocking: uses FlexIO and DMA or interrupts
- User passes struct of parameters/options to library such as:
- List of pins to correspond to output bits
- Data and clock pin polarity
- How the source data is organized (nibbles, 8bit, 16bit, 32bit)
- Options to swap output order of bytes and nibbles
- Options to discard MSBs or LSBs for odd interface widths
- Total transfer size may be limited to multiples of 32 bytes
If your data pins are contiguous and in order (with respect to FlexIO pin ordering, not Teensy pin numbers), a more efficient process could be used that skips the buffering step and uses the source data without reordering bits, which could be done with nearly zero CPU usage or lag. But this wouldn't be a big deal unless you need maximum speed.
There would be some restriction on the available pins. They all have to be from a single FlexIO peripheral, and the clock pin (if desired) has to have a lower or higher FlexIO pin number than all the data pins. Some documentation to show possible pin configurations would be needed. The maximum number of pins would be as follows:
- T4.0
- FlexIO1: 5 total (including backside pad 33), all contiguous
- FlexIO2: 9 total (including backside pad 32), 4 contiguous
- FlexIO3: 14 total (no DMA, more CPU usage; including backside pads 26-27), 6 contiguous
- T4.1
- FlexIO1: 9 total (including backside pads 49, 50, 52, 54), 5 contiguous
- FlexIO2: 13 total, 4 contiguous
- FlexIO3: 22 total (no DMA, more CPU usage), 20 contiguous
- MicroMod
- FlexIO1: 5 total, all contiguous
- FlexIO2: 15 total, 13 contiguous
- FlexIO3: 14 total (no DMA, more CPU usage), 6 contiguous