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Thread: ADC WM8782 on T4.1 MCLK problem

  1. #1

    ADC WM8782 on T4.1 MCLK problem

    Hi there,

    I'm trying to make work a Cirrus WM8782 based ADC board, which comes with its own clock. When plugged via secondary I2S_2 in Master mode it doesn't work, only a pattern noise comes out of the Teensy. In slave mode using the T4.1 MCLK and while the PJRC Audio Shield is plugged it works fine.

    Strange enough the WM8782 is set to 44100Hz (11.2896M 256fs) and 16bit, which is what the Teensy seems to require.

    Any idea what might be happening?

    Please find a screenshot of the waveform I get. Only LRCLK, BCLK and DIN are connected.

    Here a link of the datasheet and board used:

    Thanks in advance,
    Attached Thumbnails Attached Thumbnails Click image for larger version. 

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  2. #2
    Senior Member
    Join Date
    Jul 2020
    The AudioOutputI2S2slave class is work in progress I think - its commented out in the sources at the moment.

    The classes are named from the Teensy's point of view - ie the slave classes work with the chip in master mode as I understand it.

  3. #3
    Thank you for your time MarkT.

    Initially I made a connection mistake, assuming that the secondary I2S port would work out of the shelf with any I2S board in Master mode. Then I realised that about the existence AudioOutputI2Sslave, which works on the primary I2S. I desoldered the Teensy Shield that was there and configure the WM8782 as AudioOutputI2Sslave.

    When output is set to USB I can only hear a very dim and fuzzy/distorted signal, although recognisable as my voice (a microphone is plugged into the ADC). A user describes the same situation with another ADC board; he solved it but didn't say how.

    When trying to record in RAW nothing is written in the file. This is my main interest and I suppose it is because there is no driver for this chip in the Audio Library, but I wonder if there is no generic driver available to do it.

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