Teensy 4.1 Sweep and ADC MHz region

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HeadLess

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I'm currently working on a project in which I need to generate a sine sweep from 1MHz to 10MHz, sample the signal, and transform it into an FFT.
I thought a Teensy 4.1 Development Board would be able to do so. Since the processor has 600MHz.

My question: is Teensy 4.1 able to

-Sample 10MSPS (10MHz)
-sine sweep 1MHz-10MHz

I couldn't find that much information regarding those frequencies. Any help/info/datasheets would be helpful
 
It doesn't have a DAC, so not able to generate a signal at all. The on-chip ADCs are upto 1MSPS I believe.

Sampling at 10MSPS is no good for a 10MHz signal anyway, you need more like 30MSPS in practice and
definitely more than 20MSPS.

At 30MSPS you are limited to parallel ADCs I think, perhaps with DMA on the GPIO to read it. Note that the
IO clock speed is much less than the internal clock speed for a fast processor.

Do you want a smooth sine sweep, or is stepped allowed? Do you want a log or linear sine sweep? Often
a DDS chip would be used for this sort of signal generation. A smooth log sweep is probably beyond a
standard DDS chip and would need to be software generated via a fast DAC.

Have you any idea about bit-depth or SNR required? Number of total samples to store? Size of FFT?
 
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