Audio library and ADAU1761 codec

atok

Member
I'm trying to get ADAU1761 codec working with Audio library. I got everything connected, generated the configuration using SigmaStudio, exported, loaded the registers and program onto the codec and even got the PLL lock there but I'm getting no analog output signal. I expect the problem to be in my hardware or in the codec configuration so I asked on a Analog Devices support forum ( https://ez.analog.com/dsp/sigmadsp/f/q-a/552701/no-output-from-adau1761 ).

My question to this group is: what are the limitations I should be aware of while fighting with this?
On the Teensy side I'm mostly talking over i2c and generating clocks while trying to generate test sound on the DSP so i2s should not play a role yet.

I know that Audio library uses 16 bits, LRCLK 44.1 kHz (4417.65 Hz), MCLK 11.29 Mhz, BCLK 2.82 Mhz. The closest setting I got on ADAU1761 looks like this:
2021-12-04 17_55_41-Analog Devices - SigmaStudio - [sin-gen.dspproj].png

I don't understand why PLL needs this fractional set-up, though everything should match well. I'm also worried about sending MCLK over a dupont jumper

ADAU1761: https://pl.mouser.com/datasheet/2/609/ADAU1761-1502717.pdf
 
I'm trying to get ADAU1761 codec working with Audio library. I got everything connected, generated the configuration using SigmaStudio, exported, loaded the registers and program onto the codec and even got the PLL lock there but I'm getting no analog output signal. I expect the problem to be in my hardware or in the codec configuration so I asked on a Analog Devices support forum ( https://ez.analog.com/dsp/sigmadsp/f/q-a/552701/no-output-from-adau1761 ).

My question to this group is: what are the limitations I should be aware of while fighting with this?
On the Teensy side I'm mostly talking over i2c and generating clocks while trying to generate test sound on the DSP so i2s should not play a role yet.

I know that Audio library uses 16 bits, LRCLK 44.1 kHz (4417.65 Hz), MCLK 11.29 Mhz, BCLK 2.82 Mhz. The closest setting I got on ADAU1761 looks like this:
View attachment 26785

I don't understand why PLL needs this fractional set-up, though everything should match well. I'm also worried about sending MCLK over a dupont jumper

ADAU1761: https://pl.mouser.com/datasheet/2/609/ADAU1761-1502717.pdf

I'd try without the PLL.
And, the T4 (Which Teensy do you use?) uses exactly 44100Hz. It has its own high precision audio, low jitter PLL.
MCLK over a dupont may not work. I never had luck with this.. perhaps try to add a series resistor...100..300 OHM or such..
 
I'm using Teensy 4.1. Will try with a shorter, soldered on wire instead of dupont and disabled PLL.
Also, after reading through documentation it seems like a lower multiplayer is needed, for 44100Hz the right setting would be 256x (I think).
44100 x 256 = 11289600

I'm starting to thing that without getting the i2s right the codec might lock up so started looking at those to:
2021_12_05_13_08_17_Analog_Devices_SigmaStudio_sin_gen.dspproj_.png

Any ideas what those should be?
 
Sorry for double posting BUT... disabling the PLL, setting "Input master clock frequency" to 256x fs, setting SDATA mode to "Slave" and disabling the DSP altogether in registers did the trick.
View attachment 26796
 
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