5V logic clock to teensy 3,3V digital pin

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Frukost

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As part of a bigger build, I want to be able to receive logic 5V clock to a T4.0 digital pin. I've taken a look at https://next-hack.com/index.php/2017/09/15/how-to-interface-a-5v-output-to-a-3-3v-input/ and the amount of alternatives are a bit overwhelming. For my preferences regarding space and cost, I'm leaning towards this solution:

A5I16.png

(Full details in link above).

I just wanted to check with you if you see any obvious caveats, or have other thoughts on this? Thanks in advance.
 
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As part of a bigger build, I want to be able to receive logic 5V clock to a T4.0 digital pin. I've taken a look at https://next-hack.com/index.php/2017/09/15/how-to-interface-a-5v-output-to-a-3-3v-input/ and the amount of alternatives are a bit overwhelming. For my preferences regarding space and cost, I'm leaning towards this solution:

View attachment 27027

(Full details in link above).

I just wanted to check with you if you see any obvious caveats, or have other thoughts on this? Thanks in advance.

That diagram is not a solution, its the internal circuitry of any CMOS logic input - the diodes are part of the static electricity
protection in the pad for that pin, they are very tiny and not able to handle large continuous currents.

One solution is a resistive divider. Perhaps 1k:2k2, providing approx 3:2 ratio. There are other approaches:
https://randomnerdtutorials.com/how-to-level-shift-5v-to-3-3v/
 
That diagram is not a solution, its the internal circuitry of any CMOS logic input - the diodes are part of the static electricity
protection in the pad for that pin, they are very tiny and not able to handle large continuous currents.

One solution is a resistive divider. Perhaps 1k:2k2, providing approx 3:2 ratio. There are other approaches:
https://randomnerdtutorials.com/how-to-level-shift-5v-to-3-3v/

I was thinking along the lines of emulating the CMOS circuit with regular components, but a resistive divider is perhaps enough.

I forgot to mention that the clock frequencies are in the 10 - 300 Hz range. Also, I'm using a veroboard.
 
emulating the CMOS circuit doesn't do level shifting, it just provides extra protection for the destination chip.
The source of the clock signal will be operating at high currents outside its abs-max ratings if you do that.

Go with the resistive divider - 1k:2k2 will work at moderate speeds, for highest logic speeds this might
be a problem - what frequency is this clock?
 
I recalculated the frequencies, and they will be in the neighborhood of 10 - 150 Hz. Could you please clarify the values for each resistor (I assume they depend on their position in the circuit)?
 
So not fast signals.

Code:
clock >---- 1k ----+-----> teensy pin
                   |
                   |
                  2k
                   |
                  GND
output = 2 / (1+2) * input
 
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