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Thread: Teensy 4.1 SDR capability

  1. #1
    Junior Member
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    Teensy 4.1 SDR capability

    Hello,

    I am new to the Teensy 4.1 environment mostly use raspberry pi for my projects, but hit a roadblock so to say with the pi.
    My goal is to connect a AD9866 to the pi / or teensy 4.1 it is a 12 bit ADC / DAC with a sample rate from 5 Msp to 60 Msp.
    I would like to use the teensy as a decimator / mixer and output a 1 Msp rate to a downstream computer like a pi.
    Normaly this is done with a FPGA, but it would be great if a MCU can do this because make it more flexible for software development.
    (I am not a FPGA engineer).
    Is there any example for high speed gpio with DMA? Is there any measurement done with this?

    Thanks
    Paul

  2. #2
    Senior Member
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    At 60MSPS a T4 has 10 clock cycles per sample, so no, I don't think that can fly even if you can pump the data into the processor
    via DMA (the IO clock is much slower than the processor clock, note). Down conversion would require quadrature LO and mixing to
    avoid aliasing, and 10 clock cycles (even allowing for overclocking and dual instruction issue) is not going to be enough.

    But 5MSPS is probably workable, and then you can try and push upwards to see what performance can be achieved.

    I'd also worry about 12 high speed logic signals between the AD9866 and T4 creating RFI! Many high speed RF frontend chips
    like this use LVDS pairs to communicate direct into an FPGA minimising the RF hash created on the PCB by the signalling itself, as this can
    be a limiting factor for S/N in mixed signal RF chips. LVDS signalling is so much better (much less power needed, less direct RFI and less noise
    onto the digital rails too, and longer range being impedance-matched). Its pretty standard for FPGAs to support some LVDS pairs, and
    its a natural fit for this task.

    So anyway, good screening and layout is going to be needed

  3. #3
    Junior Member
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    Hi Mark,
    Thanks for your reply, indeed 60MSPS is very high for most processors. Idea was to mix down and decimate the signal, but you need some clock cycles to do so.
    But your right will try first at 5MSPS and see how fast it can go.
    To connect the AD9866 is not a problem, there are several working examples (with FPGA that is), just using 3.3 volt unbalanced.
    I have such a board working on raspberry pi designed by a dutch radio amateur. But I was looking if the fpga could be replaced by a mcu.
    But I think it is a bridge to far for the higher frequencies.

  4. #4
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    Quote Originally Posted by paulh001 View Post
    indeed 60MSPS is very high for most processors.
    I am achieving ca. 15 CPU clocks per 16 bit read on overcklocked up to 816MHz Teensy 4.1, that gives me almost 1GBit/s traffic. In case if you send data over GPIO, it is doable on 2 CPU clocks per 16 bits transfer, that gives ca. 6GBit/s traffic. You can check GPIO6 on this CPU and Teensy 4.1. Simple write to GPIO6_DR works perfect. The only one disadvantage - CPU is fully occupied, so, I was unable to achieve such speed on DMA.

    Indeed it is tricky and very noisy in regards to PCB, so, your IC for communication should be placed almost on the legs of T4.1. I am communicating with PFGA as the pipline LVDS converter to some analog ICs.
    Last edited by was-ja; 01-09-2022 at 06:01 PM.

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