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Thread: Teensy 4.1 RAM2 questions

  1. #1
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    Teensy 4.1 RAM2 questions

    I'm having trouble getting my head around how RAM2 fits into the memory architecture. I've searched the forum but can't find answers to the questions below.

    TL;DR: What's the difference in how RAM2 and Flash behave?



    My understanding is that only RAM1 is tightly coupled. "cpu speed/4" is given as the speed of accessing RAM2.

    Is RAM2 accessed via the AXI bus (like Flash)?
    Is RAM2 cached?
    If so, what kind of access times can be expected for non-cached data?
    Should I expect similar times to accessing non-cached Flash data?
    It would be useful to have even a sense of the order of magnitude involved: e.g. 10x, 100x, 1000x cpu cycles?

    Is it possible to place instructions in RAM2? My sense is that it isn't but it would be great to have this verified.

    The T4.1 description page also mentions that RAM2 is optimized for access by DMA. Presumably the idea is that data from the outside world is passed to RAM2 via a DMA and this data can then be accessed by the CPU? So RAM2 acts as a holding place for DMA data?

    Any help with this would be appreciated.
    Thanks.
    Last edited by dmn; 01-16-2022 at 05:50 PM.

  2. #2
    Senior Member+ defragster's Avatar
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    Paul can answer the BUS question ... RAM2 diff somewhat from RAM1 that is why it is good for DMA
    Quick other notes AFAIK:
    - RAM1 runs at CPU speed
    - RAM2 is clocked at CPU/4 as noted
    - there is a 32KB DATA cache on RAM2 shared by FLASH or any QSPI chips added
    - the Linker .LD file Marks RAM2 as 'no execute' - but that could be DIY edited
    -> compiling the code to those addresses and loading it there may also be DIY?
    - There is also a 32KB CODE Cache from FLASH - perhaps it may DIY to cover code from RAM2?

  3. #3
    Senior Member PaulStoffregen's Avatar
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    Whew, so many questions. Here's a quick try to answer them all.

    edit - looks like Defragster was faster!


    Quote Originally Posted by dmn View Post
    TL;DR: What's the difference in how RAM2 and Flash behave?
    RAM2 is writable. As far as bus access is concerned, flash is read only.

    Of course flash can be programmed by a special process, but not directly writable like RAM2.


    My understanding is that only RAM1 is tightly coupled. "cpu speed/4" is given as the speed of accessing RAM2.

    Is RAM2 accessed via the AXI bus (like Flash)?
    Yes, AXI bus.


    Is RAM2 cached?
    Yes.


    If so, what kind of access times can be expected for non-cached data?
    4 cycles. It's as you said above "cpu speed/4" (which kinda make me wonder why all these questions... but trying to answer every question anyway)


    Should I expect similar times to accessing non-cached Flash data?
    It would be useful to have even a sense of the order of magnitude involved: e.g. 10x, 100x, 1000x cpu cycles?
    Flash is much slower for cache misses.

    Perhaps you could try running some tests and report the results. Or search for threads where others have tried to do so (hint, the cache works really well for most cases).


    Is it possible to place instructions in RAM2? My sense is that it isn't but it would be great to have this verified.
    The default MPU config disallows code in RAM2. It's meant as a proactive security measure. If you change the MPU config, then yes, code execution is possible. Of course, you would need valid code compiled for the specific memory address, and somehow that code needs to be placed into RAM2, so in practice quite of bit of fiddling with linker scripts and startup code would be needed. So the answer is yes, it's possible, the hardware can do it, but practically speaking it's a lot of trouble that is unlikely to be worthwhile.


    The T4.1 description page also mentions that RAM2 is optimized for access by DMA. Presumably the idea is that data from the outside world is passed to RAM2 via a DMA and this data can then be accessed by the CPU? So RAM2 acts as a holding place for DMA data?
    Yes. Most of the libraries which do DMA allocate their buffers in RAM2.

  4. #4
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    Thank you both for this information. It clarifies things for me.

    I'm just re-reading my original list of questions and I can see why it appeared repetitive Paul.
    In the instances where I asked about access times for non-cached instructions/data I actually meant cached instructions/data.
    Apologies for any confusion but you answered those questions anyway.

    Thanks.

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