I'm having trouble getting my head around how RAM2 fits into the memory architecture. I've searched the forum but can't find answers to the questions below.
TL;DR: What's the difference in how RAM2 and Flash behave?
My understanding is that only RAM1 is tightly coupled. "cpu speed/4" is given as the speed of accessing RAM2.
Is RAM2 accessed via the AXI bus (like Flash)?
Is RAM2 cached?
If so, what kind of access times can be expected for non-cached data?
Should I expect similar times to accessing non-cached Flash data?
It would be useful to have even a sense of the order of magnitude involved: e.g. 10x, 100x, 1000x cpu cycles?
Is it possible to place instructions in RAM2? My sense is that it isn't but it would be great to have this verified.
The T4.1 description page also mentions that RAM2 is optimized for access by DMA. Presumably the idea is that data from the outside world is passed to RAM2 via a DMA and this data can then be accessed by the CPU? So RAM2 acts as a holding place for DMA data?
Any help with this would be appreciated.
Thanks.
TL;DR: What's the difference in how RAM2 and Flash behave?
My understanding is that only RAM1 is tightly coupled. "cpu speed/4" is given as the speed of accessing RAM2.
Is RAM2 accessed via the AXI bus (like Flash)?
Is RAM2 cached?
If so, what kind of access times can be expected for non-cached data?
Should I expect similar times to accessing non-cached Flash data?
It would be useful to have even a sense of the order of magnitude involved: e.g. 10x, 100x, 1000x cpu cycles?
Is it possible to place instructions in RAM2? My sense is that it isn't but it would be great to have this verified.
The T4.1 description page also mentions that RAM2 is optimized for access by DMA. Presumably the idea is that data from the outside world is passed to RAM2 via a DMA and this data can then be accessed by the CPU? So RAM2 acts as a holding place for DMA data?
Any help with this would be appreciated.
Thanks.
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