Hope you'll share photos or a demo video when it's built?
I will most definitely be sharing the completed project!
Not only photos and a video, but a lossless version of the track I've been painstakingly composing directly via register values—not only as an exercise in creating never before developed techniques for producing unique audio from the chip sans post-processing, but also as a a means of polishing the driver so those techniques can be used at a high level of abstraction—as well as a GitHub repo containing the schematics for a version of the board with one's choice of spring jacks or XLR jacks in place of the 40-pin DIP slots, with all necessary files for printing the PCB, a BOM, the VHDL for the FPGA which sends all of the channels, sampled at 24bits/96KHz, via AES67 to a USB 3.2 port using Ethernet over USB (interestingly the audio must be recorded at this fidelity and sample rate to accurately capture the pseudo-random noise channel, which produces extremely fast, 17 bit audio). I also plan to write a thorough FlexIO overview and tutorial in addition to KurtE's examples, as it's one of the most undervalued and underused components of NXP's i.MX RT series, and if time allows, create and maintain a repository for highly detailed Teensy documentation.
As various arrays of chips are being used for specific purposes, I've written a driver that allows one to use these techniques at a high level of abstraction. While I will likely wait a year or two before I release source for the drivers, as I'd like to get some of my work out into the world before others begin figuring these techniques, they are free to be reverse engineered for the pleasure of the demoscene. The source for interacting with the FPGA will be available in the aforementioned repo; I'm creating this version of the board so others who would like to send a large number of audio channels to a DAW via a single cord can do so, as well as develop their own synthesizers/audio generators, without spending the outrageous, entry-level price of such a rack, which hovers around $2K.
Frustratingly, I initially intended to use an RT1176, which has nearly all of the features necessary to implement the entire project without the use of an FPGA—and because I hope (but make no assumptions!) my favorite microcontroller engineering business (��) is likely to eventually release a new iteration of their flagship product using this chip or another similarly capable chip, at which point the board would no longer need the chip, and could instead be connected to a microcontroller with a fully-fledged framework which would allow one to used additional features of the chip to control other hardware.
As plenty were available for folks who only needed a handful when I began working on the PCB, I chose this direction, and when my first prototype was roughly 75% complete, I discovered there were no long an RT1176s to be found. I intend to return to this model as soon as the chip shortage allows, but for now, I have an EP to rework and release.
The chip shortage has proven to be an enormous pain in the ass for several projects I'm developing, and I can't imagine how much more frustrating it must be for you.
Edit:
Also of note: Due to the original nature of the project, I have already begun implementing AES67 for the Teensy 4.1 over NativeEthernet. As I intend to return to using the MCU for audio transmission, I also intend to complete the AES67 library. Due to some constraints of the 4.1 I won't be able to reach the theoretical maximum number of streams over a 100Mbps connection (8, each of which typically contain 8 bidirectional channels), but I should be able to reach at least half, and as the protocol is highly efficient as regards memory bandwidth, this means 32 bidirectional 24 bit/96KHz channels can be streamed with latency well below 1 millisecond while leaving plenty of overhead for other operations.
We'll soon see what can be achieved, and I'll be more than happy if that's only 16 channels. Though current-gen SoCs with 1Gbps Ethernet interfaces are not yet widely available due to the chip shortage, they will hopefully be in high-volume production within a year's time, and due to increased on-chip memory and faster external memory speed, we should be able to get much closer to the theoretical maximum at 1Gbps, numbers close to 640 bidirectional channels—
which oughtta be enough for anyone! (I'll see myself out...)—should be feasible, if wildly unnecessary.
Once complete, if you're interested, I'd be happy create a pull request for review and possible inclusion in Teensyduino.