Max PSRAM and FLASH size for teensy 4.1

Hi Im designing my own teensy 4.1 board from the schematic provided on the website.
The PSRAM page says that each chip can be 8 megabytes, but I was wondering if I could switch it out with a 16 or ever 32 Mb chip instead. Also the Teensy 4.1 page doesn't give a limit on how big the flash memory chip can be, the image given added 128mb NOR flash. Does this flash chip have to be NOR or can I add a NAND flash chip instead? I was wondering if this is specified by the Teensy bootloader on chip or is it a limit of the MIMXRT106 chip.

Thanks!
 
The PSRAM page says that each chip can be 8 megabytes, but I was wondering if I could switch it out with a 16 or ever 32 Mb chip instead.

If someone made such a chip you probably could. But as far as I know, today 8MB is the largest chip. ApMemory has said they have no plans to make a larger version, and all other SPI / QSPI RAM chips made by other companies (at least all the ones I know) are much smaller.

But if such a hypothetical chip were found, we'd almost certainly need to edit the software to make it work. It certainly would not be automatically detected and "just work". The existing code looks specifically for the ApMemory PSRAM chip.


Also the Teensy 4.1 page doesn't give a limit on how big the flash memory chip can be, the image given added 128mb NOR flash. Does this flash chip have to be NOR or can I add a NAND flash chip instead?

LittleFS supports both NOR and NAND flash. Bigger is not necessarily always better. Larger NAND flash chips have larger minimum erase size and larger minimum page write size, so they tend to be less efficient for storing small files. The list of supported chips can be found in the readme file.

https://github.com/PaulStoffregen/LittleFS/blob/main/README.md

I believe Winbond W25Q01JV*Q is also supported, but wasn't (yet) added to the readme file.

If you stray from the list of supported chips, you will have to edit the LittleFS library code!


I was wondering if this is specified by the Teensy bootloader on chip or is it a limit of the MIMXRT106 chip.

The bootloader has nothing to do extra external chips. It only programs the main flash memory.

Regarding the size limit, the FlexSPI hardware does impose an upper limit. I believe it is 248 MByte, but it's been a while since I've played with the FlexSPI config. If you use the 2 Gbit NAND chips, you might get slightly less than the full chip's 256 MByte capacity. As I recall, the hardware has an internal limit of addressing 256 MByte and allocating 8 Mbyte for the PSRAM (even if you use only the flash chip) takes away from how much of the flash can be accessed.

If connected by slow SPI rather than fast QSPI (soldered to the bottom of Teensy 4.1), I believe SPI could theoretically access up to 4 Gbyte. Write and erase speed are about the same, but reading is much faster with QSPI / FlexSPI.
 
Agreed, the chip is only 1/4 the size of the normal 8MB PSRAM.

Whether it would actually work (as only 2MB) is a good question.

It has the same Read ID command, opcode 0x9F (on page 33) but I didn't find documentation on the bytes is returns.

It has different opcodes for 1 bit vs 4 bit mode, so once configured to 4 bit mode using opcode 0x03 and 0x02 probably won't work. Otherwise the commands look very similar, so it might be possible to make this chip work with some minor tweaks to the core library.

But of course it will still be only 1/4 the size.
 
Agreed, the chip is only 1/4 the size of the normal 8MB PSRAM.

Indeed. My mistake. I think I'll stop working on Saturday evening. I confused MBit with MB ;)

In any case, I'm looking for an elegant solution that will result in me having more memory anyway (2 to 16MB more). I read in another thread that someone suggested using the x1064 processor instead of the x1062, but as I understand it, unfortunately, it is not compatible with the project.
 
16MB using two 8MB chips is the largest supported.

To get larger external RAM, you would need to use one of the other memory types that we don't support with software for Teensy, but could theoretically be used if you design your own PCB. Maybe...

SDRAM is the hardest, because it consumes so many pins. Teensy 4.x uses some of those pins, so it's a painful conflict.

HyperRAM is the middle ground. It also uses more pins, but not nearly as many as SDRAM. Exactly which chips can work, how to connect it and how to configure FlexSPI2 to access is an open question. Maybe you can find some app notes or other info from NXP. How to integrate it with the Teensyduino software is also a difficult matter which will require a deep dive into the linker script and maybe other very low-level software stuff. These are likely to be very challenging problems to solve, so if you don't already have a very solid idea of how to do it or you enjoying the idea of climbing a very steep learning curve this probably isn't a good option.

Simply using two 8BM PSRAM chips is by far the best option.
 
16MB using two 8MB chips is the largest supported...

I think I'm able to change the assumptions and limit the memory. Alternatively, if the project develops, I'll go in the direction of my own PCB. For now, I would like to use the Teensy 4.1, as it seems to me the best solution available on the market.

By the way, thank you for developing this product.
 
By the way... the 1064 is a processor with interesting specifications. It has additional RAM, and it's a shame that another board, such as Teensy 4.2 couldn't be made with such a processor. Essentially, what is the main obstacle, aside from the fact that it simply doesn't work today with the software that is for Teensy 4.1?
 
By the way... the 1064 is a processor with interesting specifications. It has additional RAM, and it's a shame that another board, such as Teensy 4.2 couldn't be made with such a processor. Essentially, what is the main obstacle, aside from the fact that it simply doesn't work today with the software that is for Teensy 4.1?

The 1064 has 4 MB on chip FLASH - no additional memory.

and the 2MB MRAM chip is $40
 
16MB using two 8MB chips is the largest supported.

To get larger external RAM, you would need to use one of the other memory types that we don't support with software for Teensy, but could theoretically be used if you design your own PCB. Maybe...

SDRAM is the hardest, because it consumes so many pins. Teensy 4.x uses some of those pins, so it's a painful conflict.

HyperRAM is the middle ground. It also uses more pins, but not nearly as many as SDRAM. Exactly which chips can work, how to connect it and how to configure FlexSPI2 to access is an open question. Maybe you can find some app notes or other info from NXP. How to integrate it with the Teensyduino software is also a difficult matter which will require a deep dive into the linker script and maybe other very low-level software stuff. These are likely to be very challenging problems to solve, so if you don't already have a very solid idea of how to do it or you enjoying the idea of climbing a very steep learning curve this probably isn't a good option.

Simply using two 8BM PSRAM chips is by far the best option.

There are 16 MByte chips that are still 8 bit, but different footprint. Looking at the datasheet tho, it looks like they need 8 datalines(?)
But looking at the facts, it's the exact same as the 8 MByte ordinary PSRAM's. Meaning 3V, 133mhz, 8bit QSPI.

Anyone know more?
1700128222065.png
1700128252295.png
 
But looking at the facts, it's the exact same as the 8 MByte ordinary PSRAM's. Meaning 3V, 133mhz, 8bit QSPI.

I spent a few minutes reading the datasheet, as I haven't seen this particular chip until now. I don't have any experience with it, but from only the datasheet it's clearly not the same (only 8 bits wide). This chip has a DQS/DM pin which doesn't exist in PSRAM chip we currently support. It appears in all the timing diagrams, like Figure 5 on page 10.

1700129684702.png
 
Regardless of the spec details, performing octal SPI would require using the FlexSPI ports in parallel and you'd still only be getting the same amount of storage as two individual 8MB quad SPI chips, so there doesn't seem to be any net gain.
 
I spent a few minutes reading the datasheet, as I haven't seen this particular chip until now. I don't have any experience with it, but from only the datasheet it's clearly not the same (only 8 bits wide). This chip has a DQS/DM pin which doesn't exist in PSRAM chip we currently support. It appears in all the timing diagrams, like Figure 5 on page 10.

View attachment 32386
Thank you Paul for taking the time. They seem quite different after all. I found the chip by using Mousers filtering and so I filtered to the same specs as the ordinary PSRAM's to try to find alternatives. There really isn't much to choose from out there when it comes to these small PSRAM's. I hope this wont become a problem in the future.

Regardless of the spec details, performing octal SPI would require using the FlexSPI ports in parallel and you'd still only be getting the same amount of storage as two individual 8MB quad SPI chips, so there doesn't seem to be any net gain.
Yes I'd still get the same 16MByte that I would get from 2x ordinary PSRAM's. But those PSRAM's are not super easy to get a hold of in small footprints. The large ones are easy, the small ones only exist on Mouser and Mouser is not very keen to sending to China for production. This complicates things and so I'm trying to see what alternatives exist.
 
I know this is not the sought solution, but in principle, connecting more memory can be implemented in the scheme that is currently in Teensy 4.1, although there is no space for it on the PCB. Generally, you can connect multiple 8MB QSPI memory chips, as it is now, only increase the number of CS (chip select) lines, at the expense of other GPIO lines. It would also be necessary to update the extended memory support driver and that's probably all.
 
I know this is not the sought solution, but in principle, connecting more memory can be implemented in the scheme that is currently in Teensy 4.1, although there is no space for it on the PCB. Generally, you can connect multiple 8MB QSPI memory chips, as it is now, only increase the number of CS (chip select) lines, at the expense of other GPIO lines. It would also be necessary to update the extended memory support driver and that's probably all.
The "memory support driver" is a physical hardware peripheral (FlexSPI), which only supports two devices per port. It's not a case of using an MMU to trap access and handle it in software.
 
Yes I'd still get the same 16MByte that I would get from 2x ordinary PSRAM's. But those PSRAM's are not super easy to get a hold of in small footprints.

Mouser has 6827 in stock today.


Those are the tiny 3x2mm package. Two of them take a total of 12 square mm space (just the chips, not including routing traces nearby). Just 1 of that BGA chip you mentioned is 48 square mm.
 
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