breakfastquark
Member
I'm currently trying to use a PWM or GPT clock as the sampling trigger for an external ADC. In the data sheet of the IMXRT1060 in the GPTx_CR field descriptions section, I can see that there seems to be an option to use an external clock (see CLKSRC -> 011 External Clock on page 3089). Using an external clock with lower jitter could improve my SNR when sampling the ADC. However, I do have some questions as I was unable to find any further documentation on using external clocks:
- Can an external clock also be used for FlexPWM clocks? Haven't found any hint in the configuration registers so I guess no(?).
- How would you actually go about connecting an external clock source? What pin would I use and how would I have to configure that pin? My first guess was to look in the muxing options for GPT_CLK which denotes to the external GPT clock but I was unable to find anything regarding external clocks. In figure 12-1 (chapter 12: Clock and Power Management) there is an input/output to the clock generation called CLK1, is that what I am looking for?
- The documentation of the external GPT clock states that it has to be 1/4 of the peripheral as they are synchronised. What does this mean? Would this mean that the main purpose of eliminating jitter cannot be achieved as the GPT jitter is limited to the jitter of the peripheral clock after all?
I know that this has little to do with the Teensy itself but more to do with the documentation of the IMXRT1060 and me not being able to sufficiently navigate the data sheet. But maybe someone knows more about this and can point me in the right direction
Thank you in advance!
- Can an external clock also be used for FlexPWM clocks? Haven't found any hint in the configuration registers so I guess no(?).
- How would you actually go about connecting an external clock source? What pin would I use and how would I have to configure that pin? My first guess was to look in the muxing options for GPT_CLK which denotes to the external GPT clock but I was unable to find anything regarding external clocks. In figure 12-1 (chapter 12: Clock and Power Management) there is an input/output to the clock generation called CLK1, is that what I am looking for?
- The documentation of the external GPT clock states that it has to be 1/4 of the peripheral as they are synchronised. What does this mean? Would this mean that the main purpose of eliminating jitter cannot be achieved as the GPT jitter is limited to the jitter of the peripheral clock after all?
I know that this has little to do with the Teensy itself but more to do with the documentation of the IMXRT1060 and me not being able to sufficiently navigate the data sheet. But maybe someone knows more about this and can point me in the right direction
Thank you in advance!