dukeblue219
Active member
This is going to sound crazy to anyone who knows enough to answer, but has anyone attempted to essentially bit-bang an NV-DDR3 interface or similar on a modern NAND device at the lowest speed modes?
For background I have experience doing this with Teeny 3.x and 4.0 to older asynchronous flash components, even to multi-Tb devices, including bus translators in between to bring 3.3v down to 1.8. No problems with that style interface. I am well-aware that an FPGA or custom controller is the normal solution here for a product. However, this is a somewhat unique testing architecture and there is some value to me in rapidly re-using existing IP while taking advantage of the ~disposable price tag of a T4.1.
I think it should be doable down in the ~33 MHz Mode 0 regime, using all the usual Teensy fast IO tricks and the continuous 8 bit GPIO available on the T4.1, but the timing is not going to be perfect like it might be on a dedicated FPGA. Has anyone actually tried? Any underlying hardware support for reading strobed DDR-like signals?
For background I have experience doing this with Teeny 3.x and 4.0 to older asynchronous flash components, even to multi-Tb devices, including bus translators in between to bring 3.3v down to 1.8. No problems with that style interface. I am well-aware that an FPGA or custom controller is the normal solution here for a product. However, this is a somewhat unique testing architecture and there is some value to me in rapidly re-using existing IP while taking advantage of the ~disposable price tag of a T4.1.
I think it should be doable down in the ~33 MHz Mode 0 regime, using all the usual Teensy fast IO tricks and the continuous 8 bit GPIO available on the T4.1, but the timing is not going to be perfect like it might be on a dedicated FPGA. Has anyone actually tried? Any underlying hardware support for reading strobed DDR-like signals?