Hello!
I want to create a small proof of concept replacement for a PAL which I'm currently reverse engineering. This is a 20pin DIP TIBPAL16L8-25CN. Its worst case propagation delay is 25ns. The PAL is faster than the application needs, which I'm still trying to characterize. There are something like 12 or 13 inputs, and 6 outputs. The output pulses are around 340ns wide, which puts the maximum frequency around 3.5mhz +/-.
The teensy would have to recognize a change in the inputs, and either a nested if/switch/case/lookup table, determine the outputs. I could probably break the logic up so that the fast-read-loop pre-qualified the inputs.... meaning read only a few bits, and only pay the time penalty of reading the other inputs and looking up, if that initial criteria was met.
I already own a couple Teensy's. Maybe a 3.1 or 3.2?
Eventually going to write equations and write a GAL --- but would like to prove out my logic now.
Is the teensy in the ballpark capable of doing this?
Thanks!
I want to create a small proof of concept replacement for a PAL which I'm currently reverse engineering. This is a 20pin DIP TIBPAL16L8-25CN. Its worst case propagation delay is 25ns. The PAL is faster than the application needs, which I'm still trying to characterize. There are something like 12 or 13 inputs, and 6 outputs. The output pulses are around 340ns wide, which puts the maximum frequency around 3.5mhz +/-.
The teensy would have to recognize a change in the inputs, and either a nested if/switch/case/lookup table, determine the outputs. I could probably break the logic up so that the fast-read-loop pre-qualified the inputs.... meaning read only a few bits, and only pay the time penalty of reading the other inputs and looking up, if that initial criteria was met.
I already own a couple Teensy's. Maybe a 3.1 or 3.2?
Eventually going to write equations and write a GAL --- but would like to prove out my logic now.
Is the teensy in the ballpark capable of doing this?
Thanks!