After spending a long time puzzling over the wear leveling code for emulated EEPROM on the Teensy 4.1, I think I finally understand how it works, but it makes me question whether the PJRC specification of 100,000 write cycles per emulated EE address is far too low.
Per eeprom.c code, 4284 EE addresses (E2END + 1) are assigned evenly across 63 flash memory sectors (FLASH_SECTORS). Each sector is 2048 words, where each word is one index byte (derived from the EE address) and one data byte. Each successive write to an EE address, if its value has changed, stores its index and the new data value to the next unused word in the flash sector. So, there can be many copies of EE data written to the same EE address, but only the value at the highest physical address in the sector is valid. When the sector is full, the software erases the physical flash sector and writes all the valid EE index/data combinations previously stored in that sector, starting at the beginning of the sector. Is this right so far?
4284 EE addresses divided by 63 sectors gives 68 EE addresses per sector. Assuming for a moment that writes are distributed evenly, then a sector will be full after 2048/68 writes per EE address, or 30 plus a fraction on average. So, the endurance of emulated EEPROM should be roughly 30 times the endurance of the underlying flash memory.
The endurance of the Winbond W25Q64JV serial flash IC is not given in the chip specification. However, an Infineon application note says the Winbond chip, like all its close competitiors, has a minimum endurance of 100,000 program/erase cycles. Does this mean the actual endurance of emulated EE is around 3 million cycles? Or am I missing some important point?
Per eeprom.c code, 4284 EE addresses (E2END + 1) are assigned evenly across 63 flash memory sectors (FLASH_SECTORS). Each sector is 2048 words, where each word is one index byte (derived from the EE address) and one data byte. Each successive write to an EE address, if its value has changed, stores its index and the new data value to the next unused word in the flash sector. So, there can be many copies of EE data written to the same EE address, but only the value at the highest physical address in the sector is valid. When the sector is full, the software erases the physical flash sector and writes all the valid EE index/data combinations previously stored in that sector, starting at the beginning of the sector. Is this right so far?
4284 EE addresses divided by 63 sectors gives 68 EE addresses per sector. Assuming for a moment that writes are distributed evenly, then a sector will be full after 2048/68 writes per EE address, or 30 plus a fraction on average. So, the endurance of emulated EEPROM should be roughly 30 times the endurance of the underlying flash memory.
The endurance of the Winbond W25Q64JV serial flash IC is not given in the chip specification. However, an Infineon application note says the Winbond chip, like all its close competitiors, has a minimum endurance of 100,000 program/erase cycles. Does this mean the actual endurance of emulated EE is around 3 million cycles? Or am I missing some important point?