Side comments to self:
Part of the write9 code that currently runs, I have wondered if it still fails at times:
Code:
while (tx_buffer_tail_ == head) {
int priority = nvic_execution_priority();
if (priority <= hardware->irq_priority) {
if ((port->STAT & LPUART_STAT_TDRE)) {
uint32_t tail = tx_buffer_tail_;
if (++tail >= tx_buffer_total_size_) tail = 0;
if (tail < tx_buffer_size_) {
n = tx_buffer_[tail];
} else {
n = tx_buffer_storage_[tail-tx_buffer_size_];
}
port->DATA = n;
tx_buffer_tail_ = tail;
}
} else if (priority >= 256)
{
yield(); // wait
}
}
In particular the comparing the priority to the default priority for the Serial port:
if (priority <= hardware->irq_priority) {
I am wondering if some sketches may choose to change the Hardware serial ports ISR priority. If I were wanting to lower the priority for a specific sketch I would more likely simply call NVIC_SetPriority on the hardware ISR, then go and edit the core sources to lower it, as changing the core changes it for all sketches that you might build for.
So wondering if the code could simply be something like:
Code:
bool tdre_was_set_before = false;
while (tx_buffer_tail_ == head) {
int priority = nvic_execution_priority();
if ((port->STAT & LPUART_STAT_TDRE)) {
if (tdre_was_set_before) {
uint32_t tail = tx_buffer_tail_;
if (++tail >= tx_buffer_total_size_) tail = 0;
if (tail < tx_buffer_size_) {
n = tx_buffer_[tail];
} else {
n = tx_buffer_storage_[tail-tx_buffer_size_];
}
port->DATA = n;
tx_buffer_tail_ = tail;
} else {
tdre_was_set_before = true;
}
} else if (priority >= 256)
{
yield(); // wait
}
}
That is if we see TDRE set twice still with the same tx_buffer_tail, then obviously the hardware serial ISR was not called...
But maybe I am missing something?