T4 FlexIO SPI clock

DrM

Well-known member
@KurtE

In KurtE's FlexIO page at github, it seems to say the default clock rate for the FlexIO is 30MHz. And, it offers the following which seems to change the master clock for the FlexIO.

Code:
void setClockSettings(uint8_t clk_sel, uint8_t clk_pred, uint8_t clk_podf);

It seems like these arguments align with Figure 14-2. Clock tree part 1, the processor reference manual Rev 3, page 1010.

In the KurtE's FlexIOSPI there is a transaction call with a clock setting. Looking into the source code, it seems that a divider is constructed from the transaction setting and the above clock.

Now the question. In simplified terms, can a faster clock be set for the FlexIO SPI? How fast can it be? How exactly do we do that?

I would like to run the SPI at 50 MHz, that is more or less the standard for a particular generation of ADCs. But of course, if it can run still faster, that would be great. I can look for an ADC with a faster readout.

Thank you


P/S This is for a new board design.
 
@jmarsh Thank you, The call set_ck() seems like it might do it, but it is entangled with the video controls. Do you have an example code that only sets the clock?

Or putting it another way, for the call from @KurtE , to set a given frequency, what are the settings for clk_sel, uint8_t clk_pred, and uint8_t clk_podf? And for purposes of the FlexIOSPI, what is the fastest it can be set to?
 
I think from the look of the parameters used in KurtE's code, his function only allows selecting one of the main clock sources and setting the dividers (so the final clock speed will be some factor of the source clock).
The code in my set_clk function allows any rate expressed as a fraction of 24MHz. So for example if num=3 and den=2, the configured clock speed will be 24 * 3 / 2 = 36 MHz. It's not tied into anything explicitly related to the video output, the clock source that it configures (PLL5) is referred to in the hardware definitions as the video PLL but it can be used for any purpose and is unlikely to be used by any other module in the chip, so safe to set to any desired speed.
 
@jmarshm, oh, ok, great, thank you. What are the ranges of values for num and den? is there a particular meaning for the names num and den that would help me understand the code?
 
Ahh, of course. Toooo simple. And yet, why not just enter a frequency and let it figure it out? Some other lower level call like set_clk_(..) can get the nitty gritty.

Thank you.
 
Ahh, of course. Toooo simple. And yet, why not just enter a frequency and let it figure it out? Some other lower level call like set_clk_(..) can get the nitty gritty.

Thank you.

Probably because there are a set of divisors that define the possible values, as opposed to being able to set any desired frequency. Best to review the code to understand the limits.
 
Frequencies aren't always whole numbers, using a numerator+denominator lets any rational number be used. For example the common VGA modes use a pixel clock of 25.1748251748...MHz so numerator=150 and denominator=143 (24*150/143 = 25.1748...).
If you wanted to pass an integer frequency value, pass it as numerator and use 24 for denominator.
 
@jmarsh Thank you, that of course makes perfect sense. It's video. I was thinking only about the spi interface. The original question was to try to increase the limit on the FlexIO SPI from 30MHz.

Here is a new ADC that I am really excited about, https://www.ti.com/product/ADS9218

It's 18 bits, 10MHz, two channel simultaneous sampling, and data comes back on two digital lines. That means it needs something like a dual channel SPI at 200MHz. Do you think the FlexIO could do that? How about two of these in parallel, four simultaneous input lines?

Thank you again.
 
This ADC uses an interface I haven't heard of before, called serial LVDS (low-voltage differential signal). Each output is actually a differential pair, so I think you would need an LVDS receiver to translate this to signals that could connected to Teensy. Analog has a whole series of interface ICs for LVDS.
 
That means it needs something like a dual channel SPI at 200MHz. Do you think the FlexIO could do that?

Seems unlikely.

It's been a while since I've looked at FlexIO, but my recollection is it samples the SCK signal using the FlexIO clock. So the FlexIO needs to be at least some multiple (or higher) of the SCK clock. I'm not sure what that multiple is... but I'd be surprised if it's less than 4. If so, you'd need FlexIO at 800 MHz. I'm pretty sure it can't possibly run that fast.

FlexSPI2 which connects to the bottom pads on Teensy 4.1 for adding memory chips is probably your only hope of anything near that speed.
 
@Paul Thank you. So, any way it turns out to be yet another part that is not available.
 
This ADC uses an interface I haven't heard of before, called serial LVDS (low-voltage differential signal). Each output is actually a differential pair, so I think you would need an LVDS receiver to translate this to signals that could connected to Teensy. Analog has a whole series of interface ICs for LVDS.

LVDS is pretty standard for high speed digital interfaces, for instance its typically supported by large FPGAs. At speeds upto 480Mbps like this chip uses standard 5V or 3.3V logic cannot be made to work reliably without using transmission lines, and at 3.3V swing across 100 ohms that's 33mA or so per logic signal, which gets very power hungry. LVDS uses 0.35V swings to greatly reduce the power consumed as well as the digital noise generated. It has to be differential to give a reasonable noise-margin from picking up noise.

Laptop displays are typically driven by LVDS, typically 4 or 8 pairs of LVDS data at 600MHz or so.
 
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