Teensy 4.1 SPI (as master) works fine (signals come out).
I have read: "only SPI master is supported".
But I would need also a second SPI as SPI slave.
Does anybody have a SPI slave implementation (at best with using DMA) for the Teensy 4.1?
Why do I need?
I want to connect a "Device Under Test" (DUT, external board) via SPI. But with a long cable,
the SCLK is "out of sync" on the MCU when receiving. I want to "compensate the round-trip delay" by using a DUAL-SPI approach:
- on device as SPI Tx (only), as master
- a second SPI Rx (only), as a slave
- the SCLK (clock) is fed back from far-end (external board) to the slave Rx, so that the delay caused
by the cable, the response delay on external chip... is "eliminated", the SLCK on Rx is delayed in a similar way as the cable and far-end chip would do
(so that SPI Rx is "in sync" with SCLK)
Therefore, I would need a second SPI peripheral, but running in slave mode.
How to do? How to modify the code...? Or: do you have it already?
I have read: "only SPI master is supported".
But I would need also a second SPI as SPI slave.
Does anybody have a SPI slave implementation (at best with using DMA) for the Teensy 4.1?
Why do I need?
I want to connect a "Device Under Test" (DUT, external board) via SPI. But with a long cable,
the SCLK is "out of sync" on the MCU when receiving. I want to "compensate the round-trip delay" by using a DUAL-SPI approach:
- on device as SPI Tx (only), as master
- a second SPI Rx (only), as a slave
- the SCLK (clock) is fed back from far-end (external board) to the slave Rx, so that the delay caused
by the cable, the response delay on external chip... is "eliminated", the SLCK on Rx is delayed in a similar way as the cable and far-end chip would do
(so that SPI Rx is "in sync" with SCLK)
Therefore, I would need a second SPI peripheral, but running in slave mode.
How to do? How to modify the code...? Or: do you have it already?