Recent content by PrintyBits

At a 24 Mhz interrupt rate, there would be barely enough cycles for just the interrupts to complete without additional code, so likely the more practical answer would be to just reduce the count. As for how the numbers fall out, the interrupt latency is >=12 clock cycles(of the 600MHz CPU clock)...

It almost seems like a moot point with a fancy SAI implementation, but I have found why the PIT timer cannot be shorter than a 0.75 uS period. In the PIT library, there is a minimum 17 clock cycle value for the timer presumably to not lock up your CPU with interrupt calls for Teensy 3.x...